FPGA Acceleration of Convolutional Neural Networks (CNNs)
White Paper FPGA Acceleration of Convolutional Neural Networks Overview Convolutional Neural Networks (CNNs) have been shown to be extremely effective at complex image recognition problems.
The GROVF RDMA IP core and host drivers provide RDMA over Converged Ethernet (RoCE v2) system implementation and integration with standard Verbs API. The RDMA IP is delivered with a reference design that includes the IP subsystem itself, the 100G MAC IP subsystem, the DMA subsystem, host drivers, and example application on software. The system drivers are integrated with OFED standard Verbs API and are compatible with well-known RNIC cards and software. The IP core also provides a low-latency FPGA implementation of RoCE v2 at 100 Gbps throughput.
The solution is a soft IP implementing RDMA over Converged Ethernet protocol. It consists of FPGA IP integrated with MAC and DMA, plus the host CPU drivers. The IP is compatible with BittWare’s IA-840f and IA-420f FPGA cards featuring Altera Agilex 7 and with XUP-VV8 and XUP-P3R FPGA cards featuring AMD UltraScale+. The solution complies with Channel Adapter and RoCE v2 requirements as stated in the IB specification. The diagram on page 1 shows a simplistic architectural overview of the system. The data plane and reliable communication is hardware offloaded and the implementation does not include CPU cores in the FPGA.
The reference example consists of three parts:
Device | LUTs | On-Chip Memory |
---|---|---|
UltraScale+ VU9P | 170K | 6Mb |
Agilex 7 AGF014 | 170K | 6Mb |
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White Paper FPGA Acceleration of Convolutional Neural Networks Overview Convolutional Neural Networks (CNNs) have been shown to be extremely effective at complex image recognition problems.
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