
Dynamic Neural Accelerator from EdgeCortix
Go Back to IP & Solutions Dynamic Neural Accelerator ML Framework EdgeCortix Dynamic Neural Accelerator (DNA), is a flexible IP core for deep learning inference
The Xiphera MACsec family provides high-speed IP cores implementing the MACsec (Media Access Control security) protocol as standardized in IEEE Std 802.1AE-2018. The MACsec protocol defines a security infrastrucure for Layer 2 (as per the OSI model) traffic by assuring that a received frame has been sent by a transmitting station that claimed to send it. The traffic between stations is also encrypted to provide data confidentiality and authenticated to provide data integrity.
Typical MACsec applications require high data bandwidths such as 10G, 25G, or 40G and often benefit greatly from FPGA-based acceleration. The Xiphera MACsec IP runs on BittWare’s IA-840f and IA-420f Agilex FPGA-based PCIe cards.
Moderate resource requirements:
Performance:
Standard Compliance:
Test Vector Compliance:
The Xiphera MACsec IP uses Advanced Encryption Standard with a 128 or 256-bit key in Galois Counter Mode (AES-GCM) to protect data confidentiality, data integrity and data origin authentication. XIP1213H is best suited for data traffic on 25 Gbps links.
The original use case for MACsec is protecting communications in wired local area networks. MACsec can also be used for the following:
RS-XI-1211B | MACsec AES128-GCM |
RS-XI-1211H | MACsec AES128-GCM, high-speed |
RS-XI-1213B | MACsec AES256-GCM |
RS-XI-1213H | MACsec AES256-GCM, high-speed |
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Go Back to IP & Solutions Dynamic Neural Accelerator ML Framework EdgeCortix Dynamic Neural Accelerator (DNA), is a flexible IP core for deep learning inference
PCIe FPGA Card XUP-VVH UltraScale+ FPGA PCIe Board with Integrated HBM2 Memory 4x 100GbE Network Ports and VU37P FPGA Need a Price Quote? Jump to
Go Back to IP & Solutions TCP/IP Offload Ethernet IP The TCP/IP (Transmission Control Protocol/ Internet Protocol) is an Ethernet IP core for FPGAs
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