Network Acceleration Products

Network Acceleration

Manage, Move and Manipulate Packets at 1-400G

When are FPGAs right for network acceleration?

Many important networking functions now depend upon FPGA-based hardware acceleration. In general, such functions fall into one of four categories:

Functions evolving too quickly for ASIC solutions

Most often in security: Anti-DDoS for example. Also high-frequency trading (HFT/Fintech) where competitive algos change regularly.

Functions too new to harden into ASIC

ASICs are expensive to justify for modest-volume applications. Early-to-market speeds like 56G PAM4 enabling 400G are first available on FPGAs.

Too specialized to justify ASIC implementation

This is seen in real-time packet capture and filtering for Lawful Intercept (LI) and functional testing of high line-rate equipment in excess of 100Gbps.

Quickly emerging proprietary functionality that previously ran on CPUs

CPUs struggle handling network tasks like DPI above 10 GbE, creating a need for offload at 40+ GbE rates. Adopting an FPGA-based solution is challenging—which is why we provided reference designs and services to help.

Use Our Enterprise-Class Products
to Build Your Network Solutions

NFV

Monitoring

Custom IP

Security

Fintech

BittWare’s Suite of Network Acceleration Tools

Building a SmartNIC application in an FPGA?
Save time by starting with one of our reference designs and build on BittWare hardware:

SmartNIC Shell Reference Design

Our SmartNIC Shell is a suite of IP for creating the basics of an 100G NIC on an FPGA. It adds features like TimeServo for precision timestamping and DPDK (via Arkville) for standards-based host interaction.

Loopback Reference Design

The Loopback example provides a more basic subset of SmartNIC Shell, removing 3rd-party IP dependencies and handling the match/action core using HLS C++ (making it easy for users to modify these components).

Example Designs Built Using SmartNIC Shell or Loopback Reference Designs

These examples are free for customers with qualifying products. Contact us for details.

Click on a design to read details; we also make the detailed App Notes available for free download!

StreamSurge 100G Network Load Testing

A 100G network load testing application for BittWare’s XUP-P3R accelerator card, StreamSurge turns the card into a simple network test solution for only the cost of the hardware.

Packet Parser Built in HLS vs. P4

We built a packet parser/classifier that extracts protocol fields from packets both in P4 and HLS, and (just as with the RSS example) compared the results.

RSS Built in RTL vs. HLS

Inside the Loopback is an RSS component. Read how we built first in RTL, then in HLS—and how they compare.

Anti-DDoS Case Study

Read how BittWare customer OVHcloud uses XUP-P3R cards in their most powerful "Armor" anti-DDoS solution.

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Browse Our Network Acceleration Products

S7t-VG6

Achronix Speedster7t FPGA board with GDDR6 and QSFP-DD

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IA-840f

3/4-length PCIe with Intel Agilex and 3× QSFP-DDs

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XUP-VV8

3/4-length PCIe with Xilinx UltraScale+ and 4× QSFP-DDs

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Browse all FPGA Cards, Modules and Servers

We have a wide range of form factors and configurations, plus customization options.

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Purchase Your Cards Pre-integrated with TeraBox™

TeraBox 1100L

Single XUP-P3R with 4× 100G QSFPs plus 20× 10G SFP+

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TeraBox 1401B and 1402B

Ultra-high density; front-panel QSFP access; AMD EPYC or Intel Xeon CPUs; fits in standard-depth racks

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Got a Question?

Discuss your network acceleration needs with our technical staff.

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