
TimeServo IP Core from Atomic Rules
BittWare Partner IP TimeServo IP Core High Performance System Timer IP The TimeServo IP core by Atomic Rules is an RTL IP core that serves
Atomic Rules UDP Offload Engine (UOE) is a UDP FPGA IP Core that allows for immediate operation at 10, 25, 40, 50, or 100GbE. The UOE IP core implements the UDP standard RFC 768, including checksum, segmentation and reassembly hardware offload.
This offloads much of the work described in RFC 768 from software to hardware. In doing so, line rates of 25, 50, and 100GbE are achievable.
The UOE IP core enables application-level UDP datagrams to be concurrently sent and received on a LAN or across a network. An integral IGMPv2 multicast pre-selector removes unwanted traffic, and L4 UDP multicasts are pre-selected so that user applications don’t have to perform this function. The UOE IP core is tested for operation with popular FPGA vendors’ Ethernet MACs.
RTL sequential circuits in the UOE IP core handle the real-time interconversion of user datagrams and Ethernet frames. The core can function simultaneously as a UDP Sender and a UDP Receiver.
To send a datagram, the core is presented with a datagram and metadata describing the destination and port. If the MAC address for the destination IP address is unknown, the ARP circuit in the core resolves it. If the PDU of the datagram being sent exceeds the MTU, the core segments the datagram into fragments.
To receive, the core listens for Ethernet frames that encapsulate a UDP/IP payload. If the checksums are correct, it forms the datagram out of one or more fragments. When an entire datagram is ready, it is presented to the application logic along with its metadata.
When receiving multicast datagrams, the core preselects and delivers to the application only the host groups that have been joined by IGMP. This capability offloads the task of decoding the 228 ClassD multicast addresses to a 4-bit code encoding 16 host groups.
Atomic Rules offers UDP IP reference designs for a range of BittWare cards. Atomic Rules UOE IP Core can operate at up to 400 MHz in such cases where 25 GbE must be implemented with the smallest footprint possible.
The IP core is available in Named-Project or Site-License forms. Both versions include the elements needed for implementation, including a self-validating test bench. Most of the verification IP is also synthesizable, enabling testing to be performed at line rate, not just within a Verilog simulator.
Named-Project: Allows the product to be used on one named project from development through production using one or more bitstreams including compiled versions of the product on authorized FPGA device(s). The project SLA prohibits use on derivative projects.
Site-License: Allows the product to be used at one authorized location from development through production using one or more bitstreams including compiled versions of the product on authorized FPGA device(s). The site SLA allows the product’s use on derivative projects from the authorized location.
Core | Device | LUT | Register | BRAM | Fmax | |
---|---|---|---|---|---|---|
64B | AMD | 78K | 74K | 59 | 400MHz | |
64B | Altera (Stratix & Agilex) | 73K | 123K | 230 M20K | 500MHz (Agilex) | |
8B | AMD | 22K | 21K | 44 | 400MHz | |
8B | Altera (Stratix & Agilex) | 23K | 32K | 88 M20K | 500MHz (Agilex) |
The UDP Offload IP is compatible with all current BittWare cards with AMD UltraScale+, Intel Stratix 10 and Intel Agilex FPGAs.
Provider of FPGA IP components and solutions for networking and quality-of-time. IP offerings include Arkville data mover for high-throughput, low-latency communications between host memory and FPGA fabric logic.
Our technical sales team is ready to provide availability and configuration information, or answer your technical questions.
"*" indicates required fields
BittWare Partner IP TimeServo IP Core High Performance System Timer IP The TimeServo IP core by Atomic Rules is an RTL IP core that serves
PCIe FPGA Card 520R-MX Stratix 10 FPGA Board with HBM2 and 480Gbps Optical Input Optimized for sensor processing applications with massive real-time data ingest requirements
Meet the Powerful IA-840f: Enterprise-Class Intel Agilex Based FPGA Accelerator > Flexible, Customizable Hardware > oneAPI Software Support Buy at Mouser Tap Into the Power
PCIe FPGA Card S7t-VG6 VectorPath Accelerator Card Achronix Speedster7t FPGA board with GDDR6 and QSFP-DD Overview The S7t-VG6 VectorPath accelerator card offers a 7nm Achronix