
Introduction to BittWare’s SmartNIC Shell for Network Packet Processing
White Paper Introduction to BittWare’s SmartNIC Shell for Network Packet Processing Overview SmartNIC Shell is a complete working NIC that is implemented on a BittWare
Working alongside CPUs, FPGAs provide part of a heterogeneous approach to computing. For certain workloads, FPGAs provide significant speedup versus CPU—in this case 50x faster for machine learning inference.
FPGAs have a range of tools to best tailor to the application. The hardware fabric adapts to use only what’s needed, including hardened floating-point blocks when required. For BWNN’s weights, we used only a single bit, plus mean scaling factor, and still achieved acceptable accuracy but saving significant resources.
Power per watt is not only important at the edge, it’s in the power budget of datacenters in both space and cost of power. FPGAs can uniquely deliver the latest efficient libraries yet at far lower power per watt than CPUs.
With BittWare’s exclusive optimized OpenCL BSP, you’re able to both tap into software-orientated developers and the latest software libraries. This allowed us to quickly adapt the YOLOv3 framework, which has improved performance over older ML libraries.
We target applications when demand to process storage outpaces traditional architectures featuring CPUs.
FPGAs allow customers to create application-specific hardware implementations that exhibit the following properties:
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White Paper Introduction to BittWare’s SmartNIC Shell for Network Packet Processing Overview SmartNIC Shell is a complete working NIC that is implemented on a BittWare
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White Paper Comparing FPGA RTL to HLS C/C++ using a Networking Example Overview Most FPGA programmers believe that high-level tools always emit larger bitstreams as
White Paper Synthetic Traffic Generator Reference Design Overview Synthetic traffic generators enable lab testing of FPGA designs with network ports. There are other applications, but