HBM2 is collection of stacked DDR memories accessible in parallel to give a total bandwidth that is the aggregate of the total.
Figure 1: Stratix 10 with two HBM2 memories connected on the die
The MX Stratix 10 device used on the BittWare 520N-MX card has two HBM2 devices, each with eight DDR memories. Each DDR memory is split into two pseudo banks in order to get the bus interface down to a clock frequency the FPGA can handle, exposed as 32 independent memory channels. On the -2 speed grade device, the maximum bandwidth from the HBM2 devices is 409 GBytes/sec. – a 5x improvement over previous FPGA cards.
Figure 2: Comparison of memory bandwidth for previous OpenCL enabled FPGA cards