FPGA Accelerated NVMe Storage Solutions
White Paper FPGA-Accelerated NVMe Storage Solutions Using the BittWare 250 series accelerators Overview In recent years, the migration towards NAND flash-based storage and the introduction
Computational packet processing applications such as software-defined networking (SDN), network functions virtualization (NFV), machine learning, video transcoding, image and speech recognition, CloudRAN, and Big Data analytics may employ both wirespeed gateware functions on an FPGA in conjunction with fast operations performed in software on one or more host processor cores.
Arkville DPDK IP core from Atomic Rules provides a high throughput line-rate agnostic conduit between FPGA hardware and GPP software. Using industry-standard AXI interfaces on the FPGA side and DPDK interfaces on the software API/ABI side, Arkville provides an exceptional “out-of-the-box” solution for both hardware and software teams. Because Arkville was designed with the specific goal of accelerating and empowering DPDK, the performance is significantly higher than one of a naïve DMA implementation on an FPGA.
View a demo of Arkville 17.05 performance plots.
As shown in the block diagram, Arkville has both a hardware and software component. The hardware component is an IP core that resides in the FPGA, producing and consuming AXI streams of packets making ingress or egress. The software component is a DPDK PMD “net/ark”, the Arkville DPDK poll-mode driver. Arkville is a conduit between FPGA logic and Host user memory for bulk data movement or individual packets.
Together, an Arkville solution looks to software like a “vanilla” line rate agnostic FPGA-based NIC (without any specific MAC). DPDK applications do not need to change significantly in order to enjoy the advantages of FPGA hardware acceleration.
Atomic Rules provides Arkville example designs that may be used as a starting point for your own solutions. These include:
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