XUP-VVH PCIe Card with Xilinx Virtex UltraScale+ VU37P FPGA
PCIe FPGA Card XUP-VVH UltraScale+ FPGA PCIe Board with Integrated HBM2 Memory 4x 100GbE Network Ports and VU37P FPGA Need a Price Quote? Jump to
Seamlessly transport data between FPGA logic and host memory at up to 60 GBytes/s (480 Gbps) in each direction. Arkville provides a high-throughput, low-latency conduit between host memory and FPGA fabric logic, offloading CPU core usage, eliminating memory copies, and improving overall efficiency.
View a demo of Arkville 17.05 performance plots.
As shown in the block diagram, Arkville has both a hardware and software component. The hardware component is an IP core that resides in the FPGA, producing and consuming AXI streams of packets making ingress or egress. The software component is a DPDK PMD “net/ark”, the Arkville DPDK poll-mode driver. Arkville is a conduit between FPGA logic and Host user memory for bulk data movement or individual packets.
Together, an Arkville solution looks to software like a “vanilla” line rate agnostic FPGA-based NIC (without any specific MAC). DPDK applications do not need to change significantly in order to enjoy the advantages of FPGA hardware acceleration.
GPP/Software Specific
Atomic Rules provides Arkville example designs that may be used as a starting point for your own solutions. These include:
Device | Speed | 6LUTs | FFs | M20k | Fmax |
---|---|---|---|---|---|
Intel Agilex F-Series | -2 | 81K | 220K | 250 | 500 |
Provider of FPGA IP components and solutions for networking and quality-of-time. IP offerings include Arkville data mover for high-throughput, low-latency communications between host memory and FPGA fabric logic.
Our technical sales team is ready to provide availability and configuration information, or answer your technical questions.
"*" indicates required fields
PCIe FPGA Card XUP-VVH UltraScale+ FPGA PCIe Board with Integrated HBM2 Memory 4x 100GbE Network Ports and VU37P FPGA Need a Price Quote? Jump to
Go Back to IP & Solutions Dynamic Neural Accelerator ML Framework EdgeCortix Dynamic Neural Accelerator (DNA), is a flexible IP core for deep learning inference
White Paper Comparing FPGA RTL to HLS C/C++ using a Networking Example Overview Most FPGA programmers believe that high-level tools always emit larger bitstreams as
ARCHITECTURAL CONCEPTS NVMe High-Speed Data Capture and Recorder The Data Capture and Recording Challenge There are many streaming data sources customers want to capture or