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SEP Modules

BittWare’s exclusive SEP (serial expansion port) allows the XUPP3R to be expanded for an additional PCIe Gen3 x16 slot, additional 4 QSFPs, or connection between two XUPP3Rs. More information is available on the XUPP3R datasheet (see sidebar).

Active and Passive Cooling Options

In addition to standard active fan and heatsink cooling, the XUPP3R offers two passive options, standard and our new advanced passive cooling using heat pipes.

Passive cooling option

Advanced passive cooling option

Board Specifications

FPGA

  • Virtex UltraScale+
    • VU9P
    • Core speed grade – 2
  • Contact BittWare for VU3P FPGA options

On-board Flash

  • Flash memory for booting FPGA

External memory

  • 4 DIMM sites, each supporting*:
    • Up to 128 GBytes DDR4 x72 with ECC
    • Up to 576 Mbits dual QDR-II+ x18 (2 independent 288 Mbit banks)

Host interface

  • x16 Gen3 interface direct to FPGA

USB ports

  • Micro USB: (USB 2.0) for debug and programming FPGA and Flash

Serial expansion port (SEP)

  • Expansion interface to FPGA via 20x GTY transceivers (optional; requires second slot)
  • 14x GPIO signals to the FPGA

QSFP cages

  • 4 QSFP28 (zQSFP) cages on front panel connected directly to FPGA via 16 transceivers
  • Each supports 100GbE, 40GbE, 4x 25GbE, or 4x 10GbE and can be combined for 400GbE

Board Management Controller

  • Voltage, current, temperature monitoring
  • Power sequencing and reset
  • Field upgrades
  • FPGA configuration and control
  • Clock configuration
  • I2C bus access
  • USB 2.0
  • Voltage overrides

Cooling

  • Standard: double-width active fan and heatsink
  • Optional: double-width passive heatsink
  • Optional: double-width advanced passive cooling with heatpipes

Electrical

  • On-board power derived from 12V PCIe slot & an AUX connector (6-pin)
  • Power dissipation is application dependent

Environmental

  • Operating temperature 5°C to 35°C

Form factor

  • 3/4-length, standard-height PCIe dual-slot board
  • 9.4 x 4.37 inches

Development Tools

Application development

  • HDL/verilog
    • BittWorks II Toolkit – host, command, and debug tools for BittWare hardware
    • Xilinx Vivado® Design Suite
  • OpenCL – Xilinx SDAccel Development Environment, SDAccel Platform Release and pre-built examples for XUP-P3R

FPGA development

  • FPGA Examples – example Vivado projects