RDMA
Low-Latency RoCE v2 at 100/200Gbps
The GROVF RDMA IP core and host drivers provide RDMA over Converged Ethernet (RoCE v2) system implementation and integration with standard Verbs API. The RDMA IP is delivered with a reference design that includes the IP subsystem itself, the 100/200G MAC IP subsystem, the DMA subsystem, host drivers, and example application on software. The system drivers are integrated with OFED standard Verbs API and are compatible with well-known RNIC cards and software. The IP core also provides a low-latency FPGA implementation of RoCE v2 at 200Gbs or 100Gbps throughput.
与RNIC和软性RoCE v2兼容
200Gb/s throughput, 2µs latency
Configurable number of
RDMA queue pairs
特点
- 硬件操作的RC、XRC、RD、UC、UD服务
- 传入和传出的SEND、RDMA READ、RDMA WRITE
- 在FPGA和ECN中实现的内存保护域
- 第三方MAC和DMA IPs
- 主机上的标准Verbs API
- 使用Verbs API的动态配置
- 硬件重传和重新排序
- 可定制的IP
通过基于FPGA的SmartNIC实现RNIC的使用案例
方框图、数据表和产品细节
产品操作
The solution is a soft IP implementing RDMA over Converged Ethernet protocol. It consists of FPGA IP integrated with MAC and DMA, plus the host CPU drivers and is compatible with a variety of BittWare’s FPGA cards. The 200Gbps IP is compatible with BittWare’s IA-440i Agilex 7 I-Series FPGA card, and the 100Gbps IP is compatible with BittWare’s IA-840f and IA-420f Agilex 7 F-series cards and XUP-VV8 and XUP-P3R UltraScale+ FPGA cards. The solution complies with Channel Adapter and RoCE v2 requirements as stated in the IB specification. The diagram above shows a simplistic architectural overview of the system. The data plane and reliable communication is hardware offloaded, and the implementation does not include CPU cores in the FPGA.
详细功能列表
- 完全兼容已知的RNIC产品和软性RoCE实现（RoCE v2）。
- 100 or 200 Gb/s throughput
- 可配置的RDMA队列对
- 1023个或更多
- 200Gbps IP: under 2.7 µs software to software latency (roundtrip) and under 1 µs hardware to hardware latency (roundtrip)
- 100Gbps IP: under 2.0 µs software to software latency (roundtrip) and under 300 ns hardware to hardware latency (roundtrip)
- 硬件重传管理
- 在FPGA中实现的存储器保护域
- 使用ECN、PFC的拥堵控制
- Can work with 3rd party MAC
- 使用Verbs API的动态配置
- 在主机用户/内核空间的标准Verbs API
- 硬件实现的可靠连接（RC）、扩展可靠连接（XRC）、可靠数据报（RD）、不可靠连接（UC）和不可靠数据报（UD）。
- 传入和传出的SEND、RDMA READ、RDMA WRITE
参考设计
该参考范例由三部分组成：
- 带有参考设计的加密FPGA IPs，实现了RDMA协议
- 为基于FPGA的RDMA适配器提供标准Verbs API支持的软件驱动程序
- 建立在Verbs API之上的应用实例，展示乒乓测试结果：延迟和带宽
实施结果样本
| 器材 | LUTs | 片上存储器 |
|---|---|---|
| UltraScale+ VU9P | 170K | 6Mb |
| Agilex 7 AGF014 | 170K | 6Mb |
兼容的FPGA卡
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