Looking for SmartNIC Shell on a low-profile board? Or do you need a larger logic footprint or perhaps HBM2 memory for your application? Our board solutions include any of the UltraScale+ boards (including low-profile with HBM2) on our Xilinx PCIe boards page linked here ↗.
SmartNIC Shell is suite of IP modules for creating 100G NICs on FPGAs—so-called “smart” NICs. These components build the basics of a functioning NIC, with added features like TimeServo for precision timestamping and DPDK (via Arkville) for standards-based host interaction at high bandwidth.
It takes significant development time to build the basics of an FPGA-based NIC. We have done this work, but with user customization in mind in features like the Match/Action pipeline and P4 language support. This lets users focus their development time on customizing SmartNIC for their product’s unique value.
Block diagram of major components.
Contact BittWare for additional detailed diagrams.
This powerful component of the Shell allows for a combination of Match and Action blocks. In Match, packets are labeled in meta data as they flow through, and then any number of Actions are applied based on those labels.
While users are free to customize other parts of the Shell, most will focus on this component using the supplied IP or their own customized match/action blocks.
With BittWare boards featuring Xilinx UltraScale+ FPGAs, users have access to SDNet—a powerful development environment for hardware-accelerated software-defined networks.
Benefits include:
| Quickly Build 100G NICs | Focus your attention on your unique application, instead of re-inventing a NIC. |
| Match/Action Pipeline | Ultra-low latency pattern matching with DPDK-compatible L2 filter. User-configurable or use as a basis for further customization. |
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Standardized kernel bypass for host interaction over PCIe. SmartNIC Shell provides DPDK offload to interact with host applications. |
| TimeServo Timestamping | Precision time stamping, including 1588-compatible clock adjustments. Uses TimeServo IP from Atomic Rules. |
| Xilinx UltraScale+ FPGA | Large, powerful FPGAs with ample room for user IP. Selection of BittWare boards including traditional low-profile NIC size (XUPPL4) to 3/4-length boards with additional logic and memory options (XUPP3R). |
For configuration options, pricing, or for more information please share your contact information and we will get in touch with you.
Get in touch with us and request the SmartNIC Shell presentation, which gives additional details on SmartNIC, including future enhancements.
