When are FPGAs right for network acceleration?
Many important networking functions now depend upon FPGA-based hardware acceleration. In general, such functions fall into one of four categories:
Functions evolving too quickly for ASIC solutions
Most often in security: Anti-DDoS for example. Also high-frequency trading (HFT/Fintech) where competitive algos change regularly.
Functions too new to harden into ASIC
ASICs are expensive to justify for modest-volume applications. Early-to-market speeds like 56G PAM4 enabling 400G are first available on FPGAs.
Too specialized to justify ASIC implementation
This is seen in real-time packet capture and filtering for Lawful Intercept (LI) and functional testing of high line-rate equipment in excess of 100Gbps.
Quickly emerging proprietary functionality that previously ran on CPUs
CPUs struggle handling network tasks like DPI above 10 GbE, creating a need for offload at 40+ GbE rates. Adopting an FPGA-based solution is challenging—which is why we provided reference designs and services to help.
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BittWare’s Suite of Network Acceleration Tools
Building a SmartNIC application in an FPGA?
Save time by starting with one of our reference designs and build on BittWare hardware:
Example Designs Built Using SmartNIC Shell or Loopback Reference Designs
These examples are free for customers with qualifying products. Contact us for details.
Click on a design to read details; we also make the detailed App Notes available for free download!
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