PCIe FPGA Card
Stratix 10 AI-optimized FPGA with HBM2
AI-Optimized for High-Bandwidth, Low-Latency AI Acceleration
Designed to tackle the most demanding artificial intelligence workloads, the 520NX is a PCIe card featuring Intel’s Stratix 10 NX2100 FPGA. This revolutionary accelerator delivers a unique combination of capabilities needed to implement low latency and larger AI models:
- High-performance AI Tensor Blocks: 143 INT8 TOPS
- Deep Near-Compute Memory: up to 8GB of HBM2
- High-Bandwidth Networking: up to 600Gbps board-to-board bandwidth
The 520NX features a Board Management Controller (BMC) for advanced system monitoring and control, which greatly simplifies platform integration and management.
Intel Stratix 10 NX2100
8GB of 3D stacked HBM2
AI Tensor Blocks
Need a Customized Variant?
The 520NX is a variant of the 520N-MX with a Stratix 10 NX FPGA instead of MX. Not exactly what you're looking for? Talk to us about your exact needs as we can quickly build additional variants.
Want More Details?
Request the Hardware Reference Guide (HRG)
The HRG gives you much more detail about the card such as block diagrams, tables and descriptions.
- Intel Stratix 10 NX
- NX2100 in an F2597 package
- 8GBytes on-chip High Bandwidth Memory (HBM2) DRAM, 410 GB/s (speed grade 2)
- Core speed grade -2: I/O speed grade -2
- Contact BittWare for other Stratix 10 NX options
- 2Gbit Flash memory for booting FPGA
- 2x 288-pin DIMM slots each fitted with 16GB modules by default, i.e., 32GB total on board (options up to 256GB total)
- Contact BittWare for QDR-II+ DIMM options
- x16 Gen3 interface direct to FPGA, connected to PCIe hard IP
- 4 QSFP28 cages on front panel connected directly to FPGA via 16 transceivers
- User programmable low jitter clocking supporting 10/25/40/100GbE
- Each QSFP28 can be independently clocked
- Jitter cleaner for network recovered clocking
- 2 QSFP28s have available 100GbE MAC hard IP
- 2x edge connectors (A, B) @ 12.5G per lane (default); each supports PCIe Gen 3 x8 hard IP, GPIO, and PCIe master and optional input clocking
- 2x inner connectors (C, D) @ 25G per lane (optional); 1x 100GbE MAC hard IP per OCuLink
Board Management Controller
- Voltage, current, temperature monitoring
- Power sequencing and reset
- Field upgrades
- FPGA configuration and control
- Clock configuration
- Low bandwidth BMC-FPGA comms with SPI link
- USB 2.0
- PLDM support
- Voltage overrides
- Standard: double-width active heatsink (with fan)
- Optional: double-width passive heatsink
- Optional: double-width liquid cooling
- On-board power derived from 12V PCIe slot & two AUX connectors (one 8-pin, one 6-pin)
- Power dissipation is application dependent
- Typical max power consumption 225W
- Operating temperature: 5°C to 35°C
- Manufactured to IPC-A-610-Class 2
- RoHS compliant
- CE, FCC, UKCA & ICES approvals
- Standard-height PCIe dual-slot board
- 4.376 x 10.5 inches (111 x 266.7 mm)
- FPGA development: BIST - Built-In Self-Test for CentOS 7 provided with source code (pinout, gateware, PCIe driver & host test application)
- Application development: Supported design flows - Quartus Prime Pro (HDL, Verilog, VHDL, etc.)
- 520NX FPGA board
- USB cable (front panel access)
- Built-In Self-Test (BIST)
- 1-year access to online Developer Site
- 1-year hardware warranty
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