In Partnership with
Brought to market in partnership with LDA Technologies, the AV-870p is a PCIe Gen5 accelerator card designed to deliver extreme performance for data center and edge compute workloads.
AV-870p
High-Speed I/O and PCIe Gen5
AMD's Next-Gen Programmable Hardware
The AMD Versal Adaptive SoCs integrate networked, power-optimized cores on an adaptable platform for the most challenging compute and networking applications.
- 7nm Architecture: Versal Premium architecture combines high bandwidth and compute density on an adaptable platform.
- PCIe Gen5 Support: Data transfer speeds 2x faster than Gen4, and high-speed interface between CPUs and workload accelerators.
Versal Premium Video
7nm Architecture
The latest generation 7nm architecture combines adaptable compute engines with a breadth of hardened memory and interfacing technologies for superior performance/watt over competing 10nm FPGAs.
PCIe Gen5 Support
PCIe Gen5 supports data transfer speeds 2x higher than PCIe Gen4, providing greater performance capabilities to developers of PC interconnect, graphics adapters, and chip-level communications.
Expansion Options
This board’s default configuration includes a mezzanine card with four QSFP-DDs. The base card plus mezzanine all fit in a dual-width standard PCIe slot.
Contact us for other configuration options that utilize the expansion ports.
Ultra High-Speed Memory
With in-package HBM2e, the AV-860h provides ultra high-speed memory for compute-intensive workloads
- 32GB HBM in-package memory for
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AV-870p Block Diagram, Data Sheet and Specifications
Board Specifications
Adaptive SoC
- Versal Premium
- VP1502/ VP1552
- Core speed grade - 2
- Contact BittWare for other FPGA options
On-Board flash
- Flash memory for booting FPGA
External memory
- 2x 8GB LPDDR4 chips (16GB total) @ 4266MHz for ARM system (64 bits)
- 432 MB of ultra-low-latency GSI SRAMs (optional)
- 12x 18-bit chips
- 216-bit total bus width
Host interface
- 2x PCIe x8 Gen5 interfaces direct to FPGA, connected to PCIe Hard IP
I/O Expansion
- I/O expansion site connected to FPGA via 48x SerDes channels:
- VP1502: 12 GTYP and 36 GTM
- VP1552 : 32 GTYP and 16 GTM
- 2x ARC6-16 connectors connected to FPGA via 8x SerDes channels each (16x total)
- VP1502: 16x GTM 56Gbps channels
- VP1552: 16x GTYP 32Gbps channels
QSFP-DD Module
- Default I/O module features 4x QSFP-DD cages on front panel supporting 56G PAM4 (uses 32x SerDes)
- Additional custom modules available. Contact BittWare.
Clocking
- 2x Jitter cleaners for network recovered clocking
- 2x 1PPS (in-board)
USB
- USB access to BMC, USB-JTAG, USB-UART
Board Management Controller
- Onboard CLI
- Python, C++ API
- 200 Mbps parallel port connected to the FPGA fabric and the NOC
- USB SD Card Reader for simple OS images transfer to ARM processors
- Fast FPGA Boot Flash programming
- Temperature, voltage, current monitoring
- SNMP agent for centralized management
- Dedicated preprogrammed array of 32 MAC addresses
- I/O ports monitoring. Full QSFP, SFP, QSFP-DD access and programming through CLI and API
- CLI-based clock selection supporting custom clock configurations
Cooling
- Standard: dual-width passive heatsink
Electrical
- On-board power derived from 12V PCIe slot and 2x AUX connectors
- Power dissipation is application dependent
Environmental
- Operating temperature: 5°C to 35°C
Form factor
- Standard-height, 3/4-length, dual-width PCIe card
- 10 x 4.37 inches (254 x 111.15 mm)
Development Tools
Application development
- Supported design flows -Vivado Design Suite (HDL, Verilog, VHDL, etc.)
r0 v5
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