
Building BittWare’s Packet Parser, HLS vs. P4 Implementations
White Paper Building BittWare’s Packet Parser, HLS vs. P4 Implementations Overview One of the features of both BittWare’s SmartNIC Shell and BittWare’s Loopback Example is
Obsolete Product Notice:
This is an obsolete product and is no longer available for purchase. Contact BittWare for a recommended newer product.
The BittWare 250-M2D is an FPGA-based Computational Storage Processor (CSP) designed to meet the draft M.2 Accelerator Module Hardware Specification standard*. It is intended to operate in Glacier Point carrier cards for Yosemite servers. These feature-rich, dense servers are favored by hyperscale and cloud companies striving to improve the performance density and energy-efficiency of machine learning platforms.
The 250-M2D product features a Xilinx Kintex® UltraScale+ FPGA directly coupled to two banks of local DDR4 memory. Customers can either develop their own acceleration applications in HDL, or take advantage of pre-programmed accelerator solutions featuring IP from BittWare partner companies.
The 250-M2D is available pre-configured with compute and storage IP from our solutions partners Myrtle.ai and Eideticom
Draft specification document: https://www.opencompute.org/wiki/Server/Working
Our technical sales team is ready to provide availability and configuration information, or answer your technical questions.
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White Paper Building BittWare’s Packet Parser, HLS vs. P4 Implementations Overview One of the features of both BittWare’s SmartNIC Shell and BittWare’s Loopback Example is
BittWare customer OVHcloud built a powerful anti-DDoS solution using FPGA technology, specifically the XUP-P3R card.
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