
FPGA Acceleration of Binary Weighted Neural Network Inference
White Paper FPGA Acceleration of Binary Weighted Neural Network Inference One of the features of YOLOv3 is multiple-object recognition in a single image. We used
TK242 from Atomic Rules is a bitstream that provides lossless packet capture for up to four 100GbE streams – out-of-the-box with no FPGA programming required. The TK242 IP runs on BittWare cards with Altera® Agilex™ FPGAs. Sustaining PCIe Gen5 x16 throughput over 400 Gb/s from Ethernet to user space host memory, TK242 provides a runtime programmable 400 Gb/s RSS filter, 6-tuple, 64K entry flow-table and queue routing. All formatting – including PCAP generation – is done in hardware, offloading that function from the host CPU. High-performance timing capability includes nanosecond-resolution packet head timestamping for fusing up to four 100GbE streams into a single time-monotonic ordered stream.
BittWare offers TeraBox integrated servers perfect for building high-density capture solutions
There are many ways to leverage TK242 for your own solution. Here are a few of them:
Use it as-is: an out-of-the-box, plug-and-go packet capture solution.
Add the FPGA board, the host, plug in, and capture packets using the Atomic Rules supplied example design. The design is limited to what is demonstrated.
Point your host application code at the in-memory hugepages filled with PCAP formatted byte streams.
The example design is your starting point. Add other capabilities before, during, and after packet capture. Most features are programmed through the DPDK.org standard API.
Modify the example design to provide other functionality.
For example, each P2PCAP flow could become its own libpcap stream, feeding its own host core.
FPGA Card | IA-420f | IA-440i | IA-780i | |||
Variant | 10G x2 | 100G x2 | 100G x2 | 200G x1 | 100G x2 | 100G x4 |
QSFP-DD Signaling | 10G NRZ on lanes 1 and 2 of the 8 lanes | 100GBASE-CR4 x2 on a single QSFP-DD | 100GBASE-CR4 x2 on a single QSFP-DD | 200BASE-CR4 as 4 lanes of 56G PAM4 | 100GBASE-CR4 x2 on a single QSFP-DD | 100GBASE-CR4 x2 on each of 2 QSFP-DDs |
PCIe | Gen4 x16 | Gen 5 x16 | ||||
RSS | Yes | No | ||||
P2PCAP Engines | 4 | 8 | 4 | |||
Paced | Yes | No |
Provider of FPGA IP components and solutions for networking and quality-of-time. IP offerings include Arkville data mover for high-throughput, low-latency communications between host memory and FPGA fabric logic.
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White Paper FPGA Acceleration of Binary Weighted Neural Network Inference One of the features of YOLOv3 is multiple-object recognition in a single image. We used
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