Comparing FPGA RTL to HLS C/C++ using a Networking Example
White Paper Comparing FPGA RTL to HLS C/C++ using a Networking Example Overview Most FPGA programmers believe that high-level tools always emit larger bitstreams as
TK242 from Atomic Rules is a bitstream that provides lossless packet capture for two 100GbE streams – out-of-the-box with no FPGA programming required. The TK242 IP runs on BittWare cards with Intel® Agilex™ FPGAs. Sustaining PCIe Gen4 x16 throughput over 200 Gb/s from Ethernet to user space host memory, TK242 provides a runtime programmable 200 Gb/s RSS filter, 6-tuple, 64K entry flow-table and queue routing. All formatting – including PCAP generation – is done in hardware, offloading that function from the host CPU. High-performance timing capability includes nanosecond-resolution packet head timestamping for fusing two 100GbE streams into a single time-monotonic ordered stream.
BittWare offers TeraBox integrated servers perfect for building high-density capture solutions
There are many ways to leverage TK242 for your own solution. Here are a few of them:
Use it as-is: an out-of-the-box, plug-and-go packet capture solution.
Add the FPGA board, the host, plug in, and capture packets using the Atomic Rules supplied example design. The design is limited to what is demonstrated.
Point your host application code at the in-memory hugepages filled with PCAP formatted byte streams.
The example design is your starting point. Add other capabilities before, during, and after packet capture. Most features are programmed through the DPDK.org standard API.
Modify the example design to provide other functionality.
For example, each P2PCAP flow could become its own libpcap stream, feeding its own host core.
Provider of FPGA IP components and solutions for networking and quality-of-time. IP offerings include Arkville data mover for high-throughput, low-latency communications between host memory and FPGA fabric logic.
Our technical sales team is ready to provide availability and configuration information, or answer your technical questions.
"*" indicates required fields
White Paper Comparing FPGA RTL to HLS C/C++ using a Networking Example Overview Most FPGA programmers believe that high-level tools always emit larger bitstreams as
Article FPGA Neural Networks The inference of neural networks on FPGA devices Introduction The ever-increasing connectivity in the world is generating ever-increasing levels of data.
White Paper Introduction to BittWare’s Loopback App Note and Example Overview BittWare’s Loopback example demonstrates several things: How to fully use the Xilinx CMAC in
IA-440i 400G + PCIe Gen5 Single-Width Card Compact 400G Card with the Power of Agilex The Intel Agilex 7 I-Series FPGAs are optimized for applications