Building BittWare’s Packet Parser, HLS vs. P4 Implementations
White Paper Building BittWare’s Packet Parser, HLS vs. P4 Implementations Overview One of the features of both BittWare’s SmartNIC Shell and BittWare’s Loopback Example is
Join BittWare and Intel as we look at oneAPI™ with a focus on FPGAs. We will look at a real-world 2D FFT acceleration example which utilizes the Intel® Stratix® 10 MX including HBM2 memory on BittWare’s 520N-MX card.
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White Paper Building BittWare’s Packet Parser, HLS vs. P4 Implementations Overview One of the features of both BittWare’s SmartNIC Shell and BittWare’s Loopback Example is
PCIe FPGA Card 520R-MX Stratix 10 FPGA Board with HBM2 and 480Gbps Optical Input Optimized for sensor processing applications with massive real-time data ingest requirements
PCIe FPGA Card 250-SoC Directly Attached Accelerator & NVMe-over-Fabric Reliable transport of NVMe frames with low latency and high throughput Need a Price Quote? Jump
PCIe FPGA Card XUP-VV8 UltraScale+ FPGA PCIe Board with 4x QSFP-DDs 8x 100GbE Network Ports and VU9P/13P FPGA Need a Price Quote? Jump to Pricing