Block Diagram
Stratix 10 FPGA Board with 4x 100G
Introducing ground-breaking single precision floating point performance of up to 10 TFLOPS, the 520N is a PCIe board featuring an Intel Stratix 10 FPGA, along with four banks of DDR4 external memory. Four network ports enable dramatic FPGA-to-FPGA scaling independent of the PCIe bus, plus support for an array of serial I/O protocols operating up at 10/25/40/100GbE.
Both traditional HDL and higher abstraction C, C++ and OpenCL-based tool flows are supported. Deliverables include an optimized board support package (BSP) for the Intel OpenCL SDK.
Tool Flow Flexibility for Software- or Hardware-Based Development
Intel FPGA OpenCL Software Development Kit (SDK)
- OpenCL support for software-orientated customers
- Abstraction for faster development
- Push-button flow for FPGA executable, driver, and API
- Add optimized HDL IP cores to OpenCL designs as libraries
Hardware Description Language (HDL)
- Traditional VHDL/Verilog support for hardware-orientated customers
- Hand-code for ultimate performance
- High-Level Synthesis (HLS) available for rapid development
- FPGA card designed to support standard Intel IP cores for Stratix 10
FPGA
- Intel Stratix 10 GX
- GX2800 in an F1760 package
- L-tile with up to 26Gbps SerDes I/O
- H-tile with up to 28Gbps SerDes I/O
- Core speed grade -2: I/O speed grade -2
- Contact BittWare for other Stratix 10 GX options
On-board Flash
- 2Gbit Flash memory for booting FPGA
External memory
- Four banks of DDR4 SDRAM x 72 bits
- 8GB per bank (32GB total / 64GB version also available)
- Transfer Rate: 2400 MT/s
Host interface
- x16 Gen3 interface direct to FPGA, connected to PCIe hard IP
QSFP cages
- 4 QSFP28 cages on front panel connected directly to FPGA via 16 transceivers
- L-Tile: up to 2 100Gbps network ports
- H-Tile: up to 4 100Gbps network ports
- User programmable low jitter clocking supporting 10/25/40/100GbE
- Each QSFP28 can be independently clocked
- Jitter cleaner for network recovered clocking
- 2 QSFP28s have available 100GbE MAC hard IP
System manager
- On-board Intel USB Blaster
- Power and temperature monitoring
- Fault condition reporting to FPGA
Cooling
- Standard: double-width active heatsink (with fan)
- Optional: double-width passive heatsink
Electrical
- On-board power derived from 12V PCIe slot & two AUX connectors (one 8-pin, one 6-pin)
- Power dissipation is application dependent
- Typical max power consumption 225W
Environmental
- Operating temperature: 5°C to 35°C
Quality
- Manufactured to ISO9001:2015 IPC-A-610-Class III
- RoHS compliant
- CE, FCC & ICES approvals
Form factor
- Standard-height PCIe dual-slot board
- 4.376 x 10.5 inches (111 x 266.7 mm)
Development Tools
- FPGA development BIST – Built-In Self-Test for CentOS 7 provided with source code (pinout, gateware, PCIe driver & host test application)
- Application development Supported design flows – Intel FPGA OpenCL SDK, Intel High-Level Synthesis (C/C++) & Quartus Prime Pro (HDL, Verilog, VHDL, etc.)
Deliverables
- 520N FPGA board
- USB cable (front panel access)
- Built-In Self-Test (BIST)
- OpenCL HPC Board Support Package (BSP)
- 1-year access to online Developer Site
- 1-year hardware warranty
