
Panel Discussion: How Today’s FPGAs are Taming the Data Deluge Problem From Gen5 to AI, NOCs to RF at the Edge
Panel Discussion How Today’s FPGAs are Taming the Data Deluge Problem From Gen5 to AI, NOCs to RF at the Edge Watch the recording for
BittWare’s XUP-PL4 is a low-profile PCIe x16 card based on the Xilinx Virtex UltraScale+ FPGA. The UltraScale+ devices deliver high-performance, high-bandwidth, and reduced latency for systems demanding massive data flow and packet processing. The board offers up to 32 GBytes of memory, sophisticated clocking and timing options, and two front panel QSFP cages, each supporting up to 100 Gbps (4×25) – including 100GbE.
The XUP-PL4 also incorporates a Board Management Controller (BMC) for advanced system monitoring, which greatly simplifies platform integration and management. All of these features combine to make the XUP-PL4 ideal for a wide range of data center applications, including network processing and security, acceleration, storage, broadcast, and SigInt.
The HRG gives you much more detail about the card such as block diagrams, tables and descriptions.
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Panel Discussion How Today’s FPGAs are Taming the Data Deluge Problem From Gen5 to AI, NOCs to RF at the Edge Watch the recording for
White Paper Comparing FPGA RTL to HLS C/C++ using a Networking Example Overview Most FPGA programmers believe that high-level tools always emit larger bitstreams as
BittWare Webinar High Performance Computing with Next-Generation Intel® Agilex™ FPGAs Featuring an Example Application from Barcelona Supercomputing Center Now Available On Demand (Included is recorded
White Paper Introduction to BittWare’s SmartNIC Shell for Network Packet Processing Overview SmartNIC Shell is a complete working NIC that is implemented on a BittWare