In Partnership with
Brought to market in partnership with LDA Technologies, the AV-860h is a PCIe Gen5 accelerator card designed to deliver extreme performance for data center and edge compute workloads.
AV-811p
AI Engine and 2x the logic and memory of other Versal adaptive SoCs
AMD's Next-Gen Programmable Hardware
The AMD Versal Adaptive SoCs integrate networked, power-optimized cores on an adaptable platform for the most challenging compute and networking applications.
- 7nm Architecture: Versal Premium architecture combines high bandwidth and compute density on an adaptable platform.
- PCIe Gen5 Support: Data transfer speeds 2x faster than Gen4, and high-speed interface between CPUs and workload accelerators.
7nm Architecture
The latest generation 7nm architecture combines adaptable compute engines with a breadth of hardened memory and interfacing technologies for superior performance/watt over competing 10nm FPGAs.
PCIe Gen5 Support
PCIe Gen5 supports data transfer speeds 2x higher than PCIe Gen4, providing greater performance capabilities to developers of PC interconnect, graphics adapters, and chip-level communications.
Product Concept
The AV-811p is currently a product concept. Ask us for more details on what’s planned and how we can best match your requirements.
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Product Concepts
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AV-811p Block Diagram, Data Sheet and Specifications
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Request the Hardware Reference Guide (HRG)
The HRG gives you much more detail about the card such as block diagrams, tables and descriptions.
Board Specifications
Adaptive SoC
- Versal Premium Series
- VP1802 or VP2802
- Core speed grade - 2
- AI engines (VP2802)
- 472 AI Engine Tiles
- 118Mb AI Engine Memory
- Contact BittWare for other FPGA options
On-Board flash
- Flash memory for booting FPGA
External memory
- 48GB LPDDR4
Host interface
- PCIe Gen5 x8x8 (biifurcated) interface direct to FPGA, connected to PCIe Hard IP
QSFP-DD Module
- Optional QSFP-DD I/O module with 4x QSFP-DD cages connected to FPGA via 8x SerDes channels each (32x total)
Clocking
- 2x Jitter cleaners for network recovered clocking
- 2x 1PPS (in-board)
USB
- USB access to BMC, USB-JTAG, USB-UART
Board Management Controller
- Onboard CLI
- Python, C++ API (contact BittWare)
- 200 Mbps parallel port connected to the FPGA fabric and the NOC
- USB SD Card Reader for simple OS images transfer to ARM processors
- Fast FPGA Boot Flash programming
- Temperature, voltage, current monitoring
- SNMP agent for centralized management
- Dedicated preprogrammed array of 32 MAC addresses
- I/O ports monitoring. Full QSFP, SFP, QSFP-DD access and programming through CLI and API
- CLI-based clock selection supporting custom clock configurations
Cooling
- Standard: dual-width passive heatsink
Electrical
- On-board power derived from 12V PCIe slot and 12-pin AUX connector
- Power dissipation is application dependent
Environmental
- Operating temperature: 5°C to 35°C
Form factor
- Standard-height, 3/4-length, dual-width PCIe card
- 10 x 4.37 inches (254 x 111.15 mm)
Development Tools
Application development
- Supported design flows -Vivado Design Suite (HDL, Verilog, VHDL, etc.)
r0 v1
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