Comparing FPGA RTL to HLS C/C++ using a Networking Example
White Paper Comparing FPGA RTL to HLS C/C++ using a Networking Example Overview Most FPGA programmers believe that high-level tools always emit larger bitstreams as
Project Peaberry
Accelerator for CXL Tiered Memory on VMWare-equipped Servers
CXL Memory Tiering
VMWare provides virtualization, where having adequate system memory is critical to prevent under-utilization of the CPU. The solution, more memory, has traditionally been limited to host memory DRAM.
This is changing with CXL and tiered memory. Project Peaberry is one example where we can build an accelerator that utilizes several memory systems, including M.2 flash, to lower the cost of server memory while retaining around 90% of performance.
Our Project Peaberry acclerator, based on the IA-720i, will be available in the future. For SC24 in Atlanta, we showed a recorded demo of Project Peaberry and a presentation giving an overview of the value proposition. Get in touch with us to learn more about what’s in store!
