Comparing FPGA RTL to HLS C/C++ using a Networking Example
White Paper Comparing FPGA RTL to HLS C/C++ using a Networking Example Overview Most FPGA programmers believe that high-level tools always emit larger bitstreams as
BittWare
On-Demand Webinar
High-Performance Network Security: MACsec and IPsec on Altera™ FPGAs
Performance Options Include 100G+ on MACsec and 200G+ on IPsec
Now Available On Demand
Do you need MACsec or IPsec at line rates beyond 10 Gb/s? Getting there has just gotten easier with hardware accelerators from BittWare + IP from Xiphera and powered by Agilex 7 FPGAs from Altera! We’re talking all about it on our webinar that’s a recording of a previous event (including Q&A from the live event).
What you’ll learn:
- Use cases for point-to-point (MACsec) and over IP networks (IPsec)
- Performance of Xiphera’s implementation in a variety of situations and line rates up to 200 Gb/s
- Standards supported
- Ease of implementation: hardware interface in development tools
- Supported BittWare board options
Speakers
Seth Reinhart, Altera
Craig Petrie, BittWare
Tommi Lampila, Xiphera
