TCP/IP Offload Ethernet IP from Chevin Technology
Go Back to IP & Solutions TCP/IP Offload Ethernet IP The TCP/IP (Transmission Control Protocol/ Internet Protocol) is an Ethernet IP core for FPGAs that
PCIe FPGA Card
385A
Intel Arria 10 Low-Profile
Dual QSFP+ and DDR3
Obsolete Product Notice:
This is an obsolete product and is no longer available for purchase. Contact BittWare for a recommended newer product.
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Overview
The 385A low profile accelerator card provides a powerful PCIe computing and I/O platform for FPGA development and deployment across a range of application areas including high performance computing, image processing, and network analytics.
Key Features
Intel Arria 10 GX 1150
2x QSFP+ for 10/40 Gbps
OpenCL BSP
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Block Diagram, Data Sheet and Specifications
Specifications
FPGA
- Intel Arria 10 GX
- 1150 GX F1517 NF40 package
- Core speed grade -2: I/O speed grade -3
- Contact BittWare for other Arria 10 GX options
On-board Flash
- Flash memory for booting FPGA
On-board memory
- Two banks of DDR3 SDRAM x 72 bits
- 4GB per bank (8GB total /16GB and 32GB version also available)
- 2133MT/s per bank
Host interface
- x8 Gen3 interface direct to FPGA
QSFP cages
- 2 QSFP+ cages on front panel connected directly to FPGA via 8 transceivers
- User programmable low jitter clocking supporting 10/40 GbE
- Each QSFP can be independently clocked
- Clocking options:
- Network recovered with jitter attenuation
- QSFP clocking: user programmable, or CPRI, 1GbE
- External clock input, 1PPS input
Cooling
- Standard: single-width active heatsink (embedded fan)
- Optional: single-width passive heatsink
Electrical
- On-board power derived from 12V PCIe slot
- Power dissipation is application dependent
- Typical max power consumption 75W
Environmental
- Operating temperature: 5°C to 35°C
Quality
- Manufactured to IPC-A-610 Class 2
- RoHS compliant
Form factor
- Half-height, half-length PCIe single-slot board
- 167.6mm x 68.9 mm x 17mm
Development Tools
FPGA development
- BIST - Built-In Self-Test for CentOS 7 provided with source code (pinout, gateware, PCIe driver & host test application)
Application development
- Supported design flows - Intel FPGA OpenCL SDK, Quartus Prime Pro (HDL, Verilog, VHDL, etc.)
Deliverables
- 385A FPGA board
- USB cable (front panel access)
- Built-In Self-Test (BIST)
- OpenCL HPC Board Support Package (BSP)
- 1-year access to online Developer Site
- 1-year hardware warranty
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