PCIe FPGA Card
250-SoC
Low Profile UltraScale+ MPSoC Card
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Overview
The 250-SoC features an AMD Zynq UltraScale+ MPSoC device offering both programmable logic and 64-bit ARM processors. This powerful, feature-rich device coordinates data transfer between two 100GbE network ports, on-board DDR4 memory and a PCIe Gen 3 host interface and is ideal for data center, networking and edge compute workloads.
Key Features
2x 100GbE via 2 QSFP28
8GB DDR4
ZU19EG MPSoC: 64-bit Cortex A53 ARM Zynq UltraScale+
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Block Diagram, Data Sheet and Specifications
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Specifications
FPGA
- AMD Zynq UltraScale+
- ZU19EG FFVD1760 package
- Core speed grade -2
- Application ARM: Quad-core Cortex-A53 MPCore 1.5GHz
- Real-Time ARM: Dual-core Cortex-R5 MPCore 600MHz
- Graphics Processor: Mali-400 MP2
- Contact BittWare for other MPSoC options
On-board DDR4 SDRAM
- DDR4 SDRAM FPGA Fabric Memory
- One 4GB bank of DDR4 SDRAM x72 bits
- Transfer Rate: 2400 MT/s
- DDR4 SDRAM MPSoC Memory
- One 4GB bank of DDR4 SDRAM x72 bits
- Transfer rate: 2400 MT/s
Host interface
- x16 mechanical PCIe Gen3 capable
- Configurable as x16 up to Gen3, or two x8 PCI in bifurcated slots
QSFP cages
- 2 front panel 4-25Gbps-lane QSFP28 cages
- User programmable low jitter clocking supporting 10/25/40/100GbE
- Each QSFP28 can be independently clocked
Board control (front panel)
- RJ45 1GbE access to the ARM processor
- USB connector for UART to ARM processor
Datacenter Deployment, Health Monitoring & Reporting
- On-board power, voltage and temperature monitoring
- Field flash update via software
- SMBus controlled anti-bricking, fallback and multiboot
- SMBus access to unique board data and temperature sensor
Cooling
- Passive heatsink
Electrical
- On-card power derived from PCIe slot supplies
- Power dissipation is application dependent
- Typical FPGA power consumption ~50W
Environmental
- Operating temperature: 5°C to 35°C
Quality
- Manufactured to IPC JSTD-001 -Class 2
- RoHS compliant
Form factor
- Half-height, half-length PCIe board
- Full-height PCI bracket option
Development Tools
FPGA development
- BIST - Built-In Self-Test for CentOS 7 provided with source code (pinout, gateware, PCIe driver and host test application)
Application development
- AMD Tools - Vivado Design Suite HLx Editions: HDL and C/C++ with HLS
Deliverables
- 250-SoC FPGA board
- Built-In Self-Test (BIST)
- 1-year access to online Developer Site
- 1-year hardware warranty
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