TimeServo IP Core

Sub-Nanosecond Resolution, Sub-Microsecond Accurate, FPGA System Timer Component

Overview

The TimeServo IP core by Atomic Rules is an RTL IP core that serves the function of an FPGA’s System Timer or Clock. Although specifically designed to support the needs of line-rate independent packet timestamping, TimeServo may find use where there is the need for a high-resolution, modest-accuracy timebase. TimeServo’s PI-DPLL allows a local TCXO to be disciplined by an external 1 PPS signal to achieve excellent syntonicity.

In conjunction with timestamp-capable MACs (not included) and host-control software (as-is examples provided), TimeServo is a vital and central component of an IEEE-1588/PTP system.

Features

  • Single-component solution for providing coherent time within an FPGA
  • Operates with or without an externally provided Pulse-Per-Second (PPS) Reference
  • Flexible and independent clocks for control-plane and reference clock
  • Up to 32 outputs, each in their own clock domain
  • Outputs individually runtime switchable between three 80-bit formats
    • Binary 48.32
    • IEEE Ordinary
    • IEEE Transparent
  • Software control and observability from AXI control plane
  • Internal logical 120-bit resolution phase accumulator
  • Proportional/Integral controlled Digital Phase Locked Loop (PI-DPLL)
  • Observable output of digital Phase-Frequency Detector (PFD Monitor)

Specifications

  • Standard AXI4-Lite Control Plane Interface
  • Up to 32 80-bit time outputs, runtime switchable binary and IEEE ordinary/transparent
  • Internal logical 120-bit Reference Clock Phase Accumulator
  • Proportional/Integral controlled Digital Phase Locked Loop (PI-DPLL)
  • Nominal Settling time: 150 s (may be changed under software control)
  • Best-Case Simulated Jitter Observation +/- 2.5 ns (with 400 MHz Reference Clock)
  • Nominal Real-World Jitter Observation +/- 10 ns (with 400 MHz Reference Clock)

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Operation and Clock Limits

All operation of the TimeServo is controlled though an AXI4-Lite Memory Mapped control-plane interface. A set of defined registers controls the module and returns the status. The control and status registers are always functioning when the control plane is operational.

In all cases, time is “made” from a Reference Clock signal. This reference clock should be chosen to be of the best possible stability. Its absolute frequency is less important when the digital PLL is engaged. The reference clock increments a 120-bit phase accumulator on each edge. Logic in the TimeServo DSP section statically or dynamically adjusts the fractional increment value added at each reference clock.

In the absence of an externally supplied Pulse-Per-Second (PPS) signal; TimeServo can be set, trimmed, and nudged under software control.

In the presence of an externally supplied PPS signal, the time can be set and nudged; but the frequency trim (e.g. faster/slower) is self-controlled and updated by TimeServo.

Supporting the trend of contemporary MACs having timestamp logic separated into multiple clock domains; each of the TimeServo’s outputs may each be placed in their own clock domain; and up to 32 outputs may be generated by the component when instantiated.

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Clock Frequency Limits (MHz)

ClockMinimum (MHz)Nominal (MHz)[1]Maximum (MHz)[2]
axi_clk50125500
ref_clk100250500
now_clk_50312.5500

[1] Performance Measurements made at nominal frequency
[2] FPGA performance limits may prevent operation at Maximum frequency (e.g. Timing Closure)


Examples Provided

“As is” software control utility to set/get common settings as well as observe behavior.

“As is” example design using Arkville IP Core (Arkville NOT Included) showing application with IEEE-1588 Precision Time Protocol (PTP). (To be included in 17.11 release.)