Stratix 10 FPGA Board with HBM2 and 480Gbps Optical Input

Optimized for sensor processing applications with massive real-time data ingest requirements

520R-MX PCIe card photo

Legacy Product Notice:

This is a legacy product and is not recommended for new designs. It is still available for purchase, but development tools and software are no longer maintained for compatibility with the latest FPGA tools and operating systems. Minimum order quantities (MOQs) may apply. Contact BittWare for details.


Designed for compute acceleration of high-speed sensor data, the 520R-MX is a PCIe board featuring Intel’s Stratix 10 MX2100 FPGA with integrated HBM2 memory. The size and speed of HBM2 (up to 16GB at up to 512GB/s) enables acceleration of memory-bound applications. 48 optical receivers provide high-speed input to the FPGA, and OCuLink connectors allow expansion.

The 520R-MX features a Board Management Controller (BMC) for advanced system monitoring and control, which greatly simplifies platform integration and management.

Key Features

Intel Stratix 10 MX2100

16GB HBM2 up to 512 GB/s

48× 10Gbps optical receivers

Need a Customized Variant?

The 520R-MX is a variant of the 520N-MX with optical receivers instead of QSFPs. Not exactly what you're looking for? Talk to us about your exact needs as we can quickly build additional variants.

Block Diagram, Data Sheet and Specifications

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Request the Hardware Reference Guide (HRG)

The HRG gives you much more detail about the card such as block diagrams, tables and descriptions.



  • Intel Stratix 10 MX
    • MX2100 in an F2597 package
    • 8GBytes on-chip High Bandwidth Memory (HBM2) DRAM, 410 GB/s (speed grade 2)
    • Core speed grade -2: I/O speed grade -3
  • Contact BittWare for other Stratix 10 MX options (16GBytes HBM2, speed grades)

On-board Flash

  • 2Gbit Flash memory for booting FPGA

External memory

  • 2 288-pin DIMM slots each fitted with a 64GB DDR4-2400 LRDIMM by default, i.e., 128GB total on board (options up to 256GB total)

Host interface

  • PCIe Gen3 x16 interface direct to FPGA, connected to PCIe hard IP

Optical Receivers

  • 4 12-channel 10.3125Gbps optical receivers, each connected to the FPGA via 12 SerDes channels


  • 3 x4 edge connectors (A, B, C) @ 10.3125Gbps per lane; one lane (C) supports PCIe Gen3 x4 hard IP

Board Management Controller

  • Voltage, current, temperature monitoring
  • Power sequencing and reset
  • Field upgrades
  • FPGA configuration and control
  • Clock configuration
  • Low bandwidth BMC-FPGA comms with SPI link
  • USB 2.0
  • PLDM support


  • Double-width passive heatsink


  • On-board power derived from 12V PCIe slot & two AUX connectors (one 8-pin, one 6-pin)
  • Power dissipation is application dependent
  • Typical max power consumption 200W


  • Operating temperature: 5°C to 40°C at card inlet


  • Manufactured to IPC-A-610-Class 2
  • RoHS compliant
  • CE, FCC, UKCA & ICES-003 approvals

Form factor

  • Standard-height PCIe dual-slot board
  • 111 x 266.7 mm (4.376 x 10.5 inches)

Development Tools

  • BittWare SDK including PCIe driver, libraries, and board monitoring utilities
  • Quartus Prime Pro (HDL, Verilog, VHDL, etc.)


  • 520R-MX FPGA board
  • 1-year access to online Developer Site
  • 1-year hardware warranty

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