Building BittWare’s Packet Parser, HLS vs. P4 Implementations
White Paper Building BittWare’s Packet Parser, HLS vs. P4 Implementations Overview One of the features of both BittWare’s SmartNIC Shell and BittWare’s Loopback Example is
Obsolete Product Notice:
This is an obsolete product and is no longer available for purchase. Contact BittWare for a recommended newer product.
Introducing ground-breaking single precision floating point performance of up to 1.5 TFLOPS per device. The BittWare 510T Datacenter Co-Processor is a standard-height, dual-slot PCIe board designed to deliver fast and efficient performance per watt. The OpenCL-programmable 510T features two Intel Arria 10 FPGAs, along with four banks of DDR4 external memory per FPGA.
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White Paper Building BittWare’s Packet Parser, HLS vs. P4 Implementations Overview One of the features of both BittWare’s SmartNIC Shell and BittWare’s Loopback Example is
Panel Discussion How Today’s FPGAs are Taming the Data Deluge Problem From Gen5 to AI, NOCs to RF at the Edge Watch the recording for
PCIe Gen4 data mover IP from Atomic Rules. Achieve up to 220 Gb/s using BittWare’s PCIe Gen4 cards, saving your development team when you need more performance than standard DMA. Features: DPDK and AXI standards, work with packets or any other data format, operate at any line rate up to 400 GbE.
For a data recorder, how many drives are required for a given sustained data rate? Find the answer in this informative white paper.