S7t-VG6

Board Specifications

FPGA

• Achronix Speedster AC7t1500
  • 52.5 x52.5 package
  • 692K 6-input lookup tables (LUTs)
  • 189 Mb embedded RAM
  • 2,560 MLPs

On-board Memory

• 8x GDDR6: 8 Gbit per, 2 independent 16 bit channels per; 8 GBytes total
• One bank DDR4-2666 with ECC, up to 4 GBytes (x72)
• Flash memory for booting FPGA

Host interface

• PCIe Gen4 x16 interface direct to FPGA

External clocking

• 1 PPS and 10MHz ref clk front panel inputs

USB

• USB port for access to BMC, USB-JTAG, USB-UART
• Second USB port for daisy chain

MCIO

• MCIO on rear edge, connected to FPGA via 4x transceivers
• PCIe Gen4 Hard IP

GPIO

• 8 GPIO pins, 3.3V, single ended, direction (Tx, Rx) independently settable by FPGA per GPIO, buffers rated to 200Mbps

QSFP cages

• QSFP-DD cage on front panel
• • 56G PAM4 transceivers
  • 1x 400GbE, 2x 200GbE, 4x 100GbE or 8x 10/25/40/50GbE
  • Hard MAC and FEC
• QSFP56 cage on front panel
• • 56G PAM4 transceivers
  • 1x 200GbE, 2x 100GbE or 4x 10/25/40/50GbE
  • Hard MAC and FEC

Board management controller

• Voltage, current, temperature monitoring
• Power sequencing and reset
• Field upgrades
• FPGA configuration and control
• Clock configuration
• I2C bus access
• USB 2.0
• Voltage overrides

Cooling

• Standard: dual-width passive heatsink
• Optional: dual-width active heatsink
• Optional: dual-width liquid cooling

Electrical

• On-board power from two AUX connectors (8 pin)
• Power dissipation is application dependent
• Typical max power consumption TBD

Environmental

• Operating temperature 5°C to 35°C

Form factor

• Standard-height PCIe dual-width board

Development Tools

System development

• Software development toolkit including PCIe driver, libraries and board monitoring utilities

FPGA development

• Achronix tools—ACE Design Tools
• FPGA example projects