
Building BittWare’s Packet Parser, HLS vs. P4 Implementations
White Paper Building BittWare’s Packet Parser, HLS vs. P4 Implementations Overview One of the features of both BittWare’s SmartNIC Shell and BittWare’s Loopback Example is
Legacy Product Notice:
This is a legacy product and is not recommended for new designs. It is still available for purchase, but development tools and software are no longer maintained for compatibility with the latest FPGA tools and operating systems. Minimum order quantities (MOQs) may apply. Contact BittWare for details.
The S7t-VG6 VectorPath accelerator card offers a 7nm Achronix FPGA that is optimized for high-speed networking and fast, high-capacity memory access. Featuring a QSFP-DD (double-density) cage, the board supports up to 1x 400GbE or 4x 100GbE using the 56G PAM4-enabled Speedster®7t device. An additional QSFP port supports 2x 100GbE, and a 4x MCIO connector for expansion. Sixteen channels of GDDR6 graphics DRAM handle high-bandwidth memory requirements, providing up to 448GB/s.
The FPGA offers large logic and memory resources—up to 692K 6-input lookup tables (LUTs), and 189 Mb embedded RAM. It also provides 2,560 MLPs (machine-learning blocks).
QSFPs for 1x 400G or 6x 100G
16GB GDDR6 up to 448GB/s
7nm FPGA with 56Gbps SERDES
Craig Petrie gives a detailed explanation of the card's key features.
Generation 5.0
The HRG gives you much more detail about the card such as block diagrams, tables and descriptions.
r4 v2
Our technical sales team is ready to provide availability and configuration information, or answer your technical questions.
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