The Xilinx UltraScale FPGAs are built on 20 nm process technology and provide ASIC-like clocking for scalability, performance, and lower dynamic power. The Virtex devices feature two types of multi-gigabit transceivers: 32x 16Gb/s (GTH) and 16x 32.75 Gb/s (GTY). The GTY transceivers enable 400GbE, 100GbE, and 25GbE. The FPGA also supports up to 1,800 DSP slices. The UltraScale FPGAs provide four integrated blocks for PCI Express, supporting x8 Gen3 Endpoint and Root Port designs. Integrated blocks for 150 Gb/s Interlaken and 100 Gb/s Ethernet (100G MAC/PCS) enable simple, reliable support for Nx100G switch and bridge applications.
The XUSP3R provides a variety of interfaces for high-speed serial I/O as well as debug support. Four QSFP28 cages are available on the front panel, each supporting 100GbE, 40GbE, four 25GbE, or four 10GbE channels, for a total of up to 400 Gbps of bandwidth. The four QSFPs can also be combined for 400GbE. The QSFP channels are connected directly to the UltraScale FPGA via 32 Gb/s GTY transceivers. The QSFP cages can optionally be adapted for SFP+.
Two Gen3 x8 PCIe interfaces connect to the FPGA via 16 GTH transceivers, allowing for a x8 PCIe connection in a standard slot or two x8 interfaces in a bifurcated slot. An optional serial expansion interface provides a 16x GTH transceiver port connection to the FPGA and can be used to add serial memory, such as Hybrid Memory Cube (HMC). The expansion site can also be used to connect an additional two x8 PCIe interfaces to the FPGA via a cable assembly connecting to an adjacent board that supports PCIe bifurcation, allowing for a total of four x8 PCIe interfaces.
A USB 2.0 interface is available for debug and programming support. The board also supports timestamping with provision for a 1 PPS and reference clock input.
The XUSP3R features four DIMM sites that support standard DDR4 DIMMs and proprietary QDR-II+ DIMMs. Each DIMM site supports up to 64 GBytes of DDR4 with optional ECC or up to 72 MBytes QDR-II+ (2 banks x18). Additional on-board memory includes Flash with factory default and support for multiple FPGA images.
The XUSP3R features an advanced system monitoring subsystem, similar to those typically found on today’s server platforms. At the heart of the board’s monitoring system lies a Board Management Controller (BMC), which accepts Intelligent Platform Management Interface (IPMI) messaging protocol commands. The BMC provides a wealth of features, including control of power and resets, monitoring of board sensors, FPGA boot loader, voltage overrides, configuration of programmable clocks, access to I2C bus components, field upgrades, and IPMI messaging. Access to the BMC is via PCIe or USB. BittWare’s BittWorks II Toolkit also provides utilities and libraries for communicating with the BMC components at a higher, more abstract level, allowing developers to remotely monitor the health of the board.
BwMonitor in the BittWorks II Toolkit provides a view into the board management capabilities of your BittWare hardware.
BittWare offers complete software support for the XUSP3R with its BittWorks II software tools. Designed to make developing and debugging applications for BittWare’s boards easy and efficient, the Toolkit is a collection of libraries and applications that provides the glue between the host application and the hardware. A variety of features allow developers to take full advantage of the Xilinx UltraScale FPGA capabilities on the BittWare board, including FPGA control via PCIe, Flash programming, custom ISR scripts, and convenient control of FPGA loads. The Toolkit supports 32-bit, and 64-bit Windows and Linux platforms and can connect to the board via PCIe or USB, providing a common API no matter the connection method.
BittWare’s FPGA Development Kit (FDK) provides FPGA board support IP and integration for BittWare’s FPGA-based boards. The FDK includes FPGA components that provide preconfigured physical interfaces, infrastructure, and examples, drastically cutting development time and easily integrating into existing FPGA development environments.
Working example projects are available for each board which illustrate how to move data between the board’s different interfaces. Supported interfaces include DDR4, QDR-II+, PCIe, 10GbE, LVDS, SerDes, and Double Data Rate I/O.
|BittWare Feature||UltraScale Support|
|Program Flash||PCIe or USB|
|Configure FPGA From Flash||PCIe or USB|
|Configure FPGA Directly via USB||not supported|
|Reset FPGA||PCIe or USB|
|Access FPGA Registers, Memory Spaces From User Applications||PCIe|
|Virtual PCIe Hot-Swap||supported|
|On-board JTAG Pod||supported|
|Factory Backup Image with PCIe||supported|
|Multiple User Images in Flash||supported|
|Serial Number||PCIe or USB|
|MAC Addresses For Each Network Interface||PCIe or USB|
|BMC Voltage, Current, Temperature Sensors||PCIe or USB|
|BMC Clock Re-programming||PCIe or USB|
|BMC FPGA Core Voltage Override||PCIe or USB|
|Upgrade BMC Firmware||USB|
|Documentation||Quick-start Guide, User’s Manual, How-to Index, BMC User’s Guide|
|Examples||PCIe DMA, 10G Ethernet, DDR4 Memory, BMC Host (without using BittWare drivers)|
|XUSP3R – RW-ABBBBCD-EEFFGGHH-IJKLMNOP-QR-S-T|
0U = Commercial (0°C to 50°C)*
UltraScale Printed Wiring Board
D = Optimized for VU190 FPGA*
FPGA Type and Size
FPGA Core Speed Grade
FPGA Temperature Range
E = Extended (Tj = 0 to +100C)*
S = Standard
0 = 322.265625*
4 = 4 QSFP cages
Serial Expansion Port
Factory JTAG Header
0 = Default
6 = RoHS 6/6