All operation of the TimeServo is controlled though an AXI4-Lite Memory Mapped control-plane interface. A set of defined registers controls the module and returns the status. The control and status registers are always functioning when the control plane is operational.
In all cases, time is “made” from a Reference Clock signal. This reference clock should be chosen to be of the best possible stability. Its absolute frequency is less important when the digital PLL is engaged. The reference clock increments a 120-bit phase accumulator on each edge. Logic in the TimeServo DSP section statically or dynamically adjusts the fractional increment value added at each reference clock.
In the absence of an externally supplied Pulse-Per-Second (PPS) signal; TimeServo can be set, trimmed, and nudged under software control.
In the presence of an externally supplied PPS signal, the time can be set and nudged; but the frequency trim (e.g. faster/slower) is self-controlled and updated by TimeServo.
Supporting the trend of contemporary MACs having timestamp logic separated into multiple clock domains; each of the TimeServo’s outputs may each be placed in their own clock domain; and up to 32 outputs may be generated by the component when instantiated.
|Clock||Minimum (MHz)||Nominal (MHz)||Maximum (MHz)|
 Performance Measurements made at nominal frequency
 FPGA performance limits may prevent operation at Maximum frequency (e.g. Timing Closure)
“As is” software control utility to set/get common settings as well as observe behavior.
“As is” example design using Arkville IP Core (Arkville NOT Included) showing application with IEEE-1588 Precision Time Protocol (PTP). (To be included in 17.11 release.)