High Performance Computing BSP

The traditional OpenCL model has a host that passes data to the accelerator system over PCI Express® (PCIe). For the HPC platform, the system requires a large amount of local bulk storage for processing the data that the host sends to the accelerator. These applications require large amounts of memory bandwidth and are systems where computing power is most important. This platform is the standard platform for OpenCL accelerators.

  • 2 banks of 4 GB DDR3-1600
  • PCIe Gen2 x8

Supported Boards

Network Enabled BSP – MAC Only

The Network Enabled BSP provides raw 10G network data streams directly into and out of the FPGA’s OpenCL kernels via I/O channels, without host interaction. This provides tremendous latency and bandwidth benefits over the traditional model, which requires NIC to host to FPGA data paths.

Supported Board

Network Enabled BSP – UDP

The Network Enabled BSP provides 10GbE UDP data straight into and out of the FPGA’s OpenCL kernels via I/O channels, without host interaction. This provides tremendous latency and bandwidth benefits over the traditional model, which requires NIC to host to FPGA data paths.

  • 2 banks of DDR3-1600
  • 4 banks of QDRII+ 550 MHz
  • PCIe Gen2 x8
  • 2 UDP
  • Also available with MAC only (no UDP)

Supported Board

Custom BSPs

If you need a Board Support Package specifically tailored for your application, our design team can create a custom BSP for you using our extensive FPGA Developer’s Kit. Contact BittWare for details.

Benefits of OpenCL for FPGAs

  • Faster time-to-market using the OpenCL C-based parallel programming language as opposed to low-level hardware description language (HDL)
  • Quick design exploration by working at a higher level of design abstraction
  • Easy design re-use by re-targeting existing OpenCL C code to current and future FPGAs
  • Faster design completion by generating an FPGA implementation of OpenCL C code in a single step, bypassing the manual timing closure efforts and implementation of communication interfaces between the FPGA, host, and external memories.
  • Increased performance by offloading performance- intensive functions from the host processor to the FPGA
  • Significantly lower power than a GPU or multicore CPU by using the Altera SDK for OpenCL, which generates only the logic needed

Development Tool Support

The BittWare OpenCL BSPs are included in our OpenCL Developer’s Bundle, which includes a BittWare Arria 10 or Stratix V PCIe board, the BittWorks II system development software, the Altera Quartus II soft­ware, and the Altera SDK for OpenCL. This development bundle gives developers access to the latest generation of high-performance FPGAs on a validated PCIe board, while also significantly reducing their time­to-market by using OpenCL to develop their application.

Hardware Support

OpenCL BSPs are currently available for BittWare’s A10PL4 and S5PH-Q PCIe boards. The boards can also be integrated into a com­plete application-ready server platform.