BittWare Hardware

A10PL4 PCIe Board

BittWare’s A10PL4 is a Gen3 x8 low-profile PCIe card based on the Arria 10 FPGA, ideal for a wide range of applications, including network processing and security, compute and storage, instrumentation, broadcast, and SigInt. The board offers 8 GBytes DDR4, sophisticated clocking and timing options, and two front panel QSFP cages, each supporting up to 100 Gbps (4×25). The A10PL4 also incorporates a Board Management Controller (BMC) for advanced system monitoring, which greatly simplifies platform management. Additional I/O interfaces include USB 2.0 and SATA.

S5PH-Q PCIe Board

BittWare’s S5PH-Q is a Gen3, x8 half-size PCIe card based on the high-bandwidth, power-efficient Altera Stratix V FPGA. The S5PH-Q is a versatile and efficient solution for high-performance network processing, signal processing, and data acquisition, with up to 16 GBytes of on-board DDR3 SDRAM and optional QDRII/II+ up to 72 MB (@ 550 MHz). I/O interfaces include two front-panel QSFP+ cages for serial I/O, two SATA connectors, and timestamping support, as well as RS-232, JTAG, and USB for debug.

Tools & Support

BittWorks II Toolkit-Lite

For system development tools, BittWare offers the BittWorks II Toolkit-Lite, which is a collection of utilities for BittWare’s Arria 10 and Stratix V boards. It provides utilities for board health and power monitoring as well as burning FPGA images to Flash. The Developer’s Bundle also includes a board support package for the A10PL4 or S5PH-Q

Altera® SDK for OpenCL

The Altera® SDK for OpenCL provides a design environment enabling users to easily implement OpenCL applications on Altera’s FPGAs.

Altera Quartus II

The OpenCL Developer’s Bundle includes the Altera Quartus II software, the complete software development package for the Altera Arria 10 and Stratix V FPGAs.

BittWare is a preferred board supplier for Altera OpenCL, and Altera has certified the S5PH-Q to support the OpenCL SDK.

What Is OpenCL

What is OpenCL?

The OpenCL (Open Computing Language) standard is the first royalty-free, open standard framework that enables users to write programs that execute across heterogeneous systems including CPUs (Central Processing Units), GPUs (Graphics Processing Units), DSPs (Digital Signal Processors), and FPGAs. It allows the use of a C-based language for developing code across these different platforms.

Developed by the Khronos Group, OpenCL greatly improves speed and responsiveness for many applications, including those in defense/aerospace, communications, high end instrumentation, life sciences, and financial.

OpenCL Benefits

What Are the Benefits of OpenCL for FPGAs?

  • Faster time-to-market using the OpenCL C-based parallel programming language as opposed to low-level hardware description language (HDL)
  • Quick design exploration by working at a higher level of design abstraction
  • Easy design re-use by re-targeting existing OpenCL C code to current and future FPGAs
  • Faster design completion by generating an FPGA implementation of OpenCL C code in a single step, bypassing the manual timing closure efforts and implementation of communication interfaces between the FPGA, host, and external memories.
  • Increased performance by offloading performance-intensive functions from the host processor to the FPGA
  • Significantly lower power by using the Altera SDK for OpenCL which generates only the logic needed to deliver