Intel Arria 10 GX FPGA

Built on 20 nm process technology, the Arria 10 FPGAs feature industry-leading programmable logic that integrates a rich feature set of embedded peripherals, embedded high-speed transceivers, hard memory controllers, and protocol IP controllers. Variable-precision digital signal processing (DSP) blocks integrated with hardened floating point (IEEE 754-compliant) enable the Arria 10 to deliver floating point performance of up to 1.5 TFLOPS. The FPGA supports Gen3 PCIe x8 via hard IP blocks and provides up to 1150K equivalent LEs.

I/O Interfaces

The A10PED provides a variety of interfaces for high-speed serial I/O as well as debug support. Two 12x Avago fiber optic modules are on the front panel, supporting high-density, high-speed optical interconnects. A QSFP cage is also available on the front panel, supporting four 10GigE channels. The Avago and QSFP SerDes channels are connected directly to the Arria 10 FPGAs, thus removing the latency of external PHYs. The QSFP cage can optionally be adapted for SFP+.

Several additional interfaces also support high-speed I/O. Two Gen3 x8 PCIe interfaces connect to the FPGAs via 16 SerDes lanes, allowing for a x8 PCIe connection (to FPGA A) in a standard slot or two x8 interfaces (one to each FPGA)in a bifurcated slot. Two SerDes lanes are available via SATA connectors to connect external storage devices or provide direct board-to-board communication.

A USB 2.0 interface provides debug and programming support. The USB features a built-in Intel USB-Blaster and is connected to the Board Management Controller. The board also provides an on-board powered GPIO header.

Memory

The A10PED features four SODIMM sites, each supporting up to 8 GBytes of DDR4 with optional error-correcting codes (ECC). A Hybrid Memory Cube (HMC) provides high-performance serial memory. Additional on-board memory includes flash with factory default and support for multiple FPGA images.

Board Management Controller

Boards in BittWare’s A10 family feature an advanced system monitoring subsystem, similar to those typically found on today’s server platforms. At the heart of the board’s monitoring system lies a Board Management Controller (BMC), which accepts Intelligent Platform Management Interface (IPMI) messaging protocol commands. The BMC provides a wealth of features, including control of power and resets, monitoring of board sensors, FPGA boot loader, voltage overrides, configuration of programmable clocks, access to I2C bus components, field upgrades, and IPMI messaging. Access to the BMC is via PCIe or USB. BittWare’s BittWorks II Toolkit also provides utilities and libraries for communicating with the BMC components at a higher, more abstract level, allowing developers to remotely monitor the health of the board.

BwMonitor in the BittWorks II Toolkit provides a view into the board management capabilities of your BittWare hardware.

Development Tools

BittWorks II Toolkit

BittWare offers complete software support for the A10PED with its BittWorks II software tools. Designed to make developing and debugging applications for BittWare’s boards easy and efficient, the Toolkit is a collection of libraries and applications that provides the glue between the host application and the hardware. A variety of features allow developers to take full advantage of the Arria 10 FPGA capabilities on the BittWare board, including FPGA control via PCIe, Flash programming, custom ISR scripts, and convenient control of FPGA loads. The Toolkit supports 64-bit Windows and Linux platforms and can connect to the board via PCIe or USB, providing a common API no matter the connection method.

FPGA Development Kit

BittWare’s FPGA Development Kit provides FPGA board support IP and integration for BittWare’s Intel FPGA-based boards. The FPGA DevKit includes FPGA components that provide preconfigured physical interfaces, infrastructure, and examples, drastically cutting development time and easily integrating into existing FPGA development environments.

Working example projects are available for each board which illustrate how to move data between the board’s different interfaces. Supported interfaces include DDR4, PCIe, 10GigE, LVDS, SerDes, and Double Data Rate I/O. All example projects are available on BittWare’s Developer Site.

BittWare Firmware and Network Solutions Partners

BittWare offers firmware for the Arria 10 FPGA on the A10 family PCIe boards, targeted specifically for networking applications. BittWare’s FPGA framework provides a solid base for your application, including the following:

  • 10GigE MAC
  • PCIe multi-channel DMA engines
  • DDR4 SDRAM controllers
BittWare has also partnered with several companies to offer solutions for networking and financial acceleration:
  • Algo-Logic: Market feed handler and low latency gateway libraries, MAC, TOE
  • Argon Design: Design services specializing in multimedia and FPGA-based high performance trading
  • Atomic Rules: Custom IP development, example UDP, precision timestamping, PCIe, networking
  • Enyx: UOE, TOE, book building IP, order management IP, Market Feed Handler
  • Intilop: Ultra low latency TOE, UOE, and MAC
  • LDA Technologies: 25 GbE Networking enclosures for PCI Express compliant FPGA board platforms
  • LeWiz: Ultra low latency, multi-session TOE IP cores
  • PolyBus: Infiniband link layer and transport layer
  • Tamba Networks: Ultra low latency 10/40/100 GigE MAC + PCS, TOE

FPGA

  • Intel Arria 10 GX FPGA
  • High-performance, multi-gigabit SerDes transceivers @ up to 17 Gbps
  • Up to 1150 logic elements available
  • Up to 53 Mb of embedded memory
  • 1.6 Gbps LVDS performance
  • Up to 3,376 18×19 variable-precision multipliers

On-Board Memory

  • Flash memory for booting FPGA

Hybrid Memory Cube (HMC)

  • Up to 2 GByte Hybrid Memory Cube connected to each FPGA via 16x SerDes

Optional SODIMM Memory

  • 2 per FPGA; can be any of the following:
  • DDR4: x72 w/ECC

PCIe Interface

  • Two x8 Gen1, Gen2, Gen3 interfaces direct to FPGAs: one x8 interface (to FPGA A) in a standard slot; two x8 interfaces (one to each FPGA) requires bifurcated slot

USB Header

  • Micro USB port (USB 2.0) for debug and programming FPGA and Flash
  • Built-in Altera USB-Blaster

Avago Fiber Optic

  • Two 12x Avago fiber optic modules, connected to the FPGAs via 12 SerDes channels each

QSFP Cages

  • QSFP28 (zQSFP) cage on front panel connected directly to each FPGA via 2 SerDes (no external PHY)
  • Supports 4x 10GigE
  • Backward compatible with QSFP and can be optionally adapted for use as SFP+

Serial ATA

  • Two SATA connectors, connected to FPGAs

Board Management Controller

  • Voltage, current, temperature monitoring
  • Power sequencing and reset
  • Field upgrades
  • FPGA configuration and control
  • Clock configuration
  • I2C bus access
  • USB 2.0 and JTAG access
  • Voltage overrides

Size

  • Full-length, standard-height, double-wide PCIe slot card

Development Tools

System Development

  • BittWorks II Toolkit – host, command, and debug tools for BittWare hardware; Matlab API; source code porting kit also available

FPGA HDL Development

  • FPGA Development Kit
    • Physical interface components
    • Board, I/O, and timing constraints
    • Example Quartus projects
    • Software components and drivers
  • Altera Tools
    • Quartus II software, including Qsys
A10PED-RW-A-BBBBCDEF-G-HHII-J-KKKKLMNO-P-QQRR-0-0-UVWXYZ-AB
RW Ruggedization0U = Commercial (0°C to 50°C)*
A A10 Printed Wiring Board
  • A = Optimized for 660 FPGA*
  • B = Optimized for 1150 FPGA †
BBBB Arria 10 A Type and Size
  • 066X = Arria 10 GX 660*
  • 115X = Arria 10 GX 1150 †
C Arria 10 A Transceiver Speed
  • 0 = None
  • 3 = 14.2 Gbps for GX*
  • 4 = 12.5 Gbps for GX
D Arria 10 A Temperature Range
  • E = 0C to 100C*
E Arria 10 A Core Speed Grade
  • 1 = Faster
  • 2 = Standard*
  • 3 = Slower
F Arria 10 A Power Options
  • L = Low static power
  • S = Standard*
G FPGA A Front Panel Optics
  • N = Empty sockets*
  • I = Rx module, empty Tx socket
  • O = Tx module, empty Rx socket
  • B = Bi-directional
HH FPGA A SODIMM A
  • 0 0= None
  • E3 = DDR4 4GB x72*
  • E4 = DDR4 8GB x72
II FPGA A SODIMM B
  • 0 0= None
  • E3 = DDR4 4GB x72*
  • E4 = DDR4 8GB x72
J HMC
  • 0 = None
  • 1 = 2GB*
KKKK Arria 10 B Type and Size
  • 066X = Arria 10 GX 660
  • 115X = Arria 10 GX 1150
L Arria 10 B Transceiver Speed
  • 3 = 14.2 Gbps for GX*
  • 4 = 12.5 Gbps for GX
M Arria 10 B Temperature Range
  • E = 0C to 100C*
N Arria 10 B Core Speed Grade
  • 1 = Faster
  • 2 = Standard*
  • 3 = Slower
O Arria 10 B Power Options
  • L = Low static power
  • S = Standard*
P FPGA B Front Panel Optics
  • N = Empty sockets*
  • I = Rx module, empty Tx socket
  • O = Tx module, empty Rx socket
  • B = Bi-directional
QQ FPGA B SODIMM A
  • 0 0= None
  • E3 = DDR4 4GB x72*
  • E4 = DDR4 8GB x72
RR FPGA B SODIMM B
  • 0 0= None
  • E3 = DDR4 4GB x72*
  • E4 = DDR4 8GB x72
U Timing
  • 0 = On-board circuits only
  • S = Front panel SMAs*
V Oscillator
  • A = Adjustable TCXO†
  • T = TCXO*
W Auxilliary Oscillator
  • 2 = None*
X Heatsink – FPGA
  • A = Active*
  • P = Passive
Y Heatsink – HMC
  • A = Active
  • P = Passive*
AZ Mechanical Options
  • 0 = No stiffener
  • S = Standard stiffener*
A Misc. Configuration
  • 0 = Default
B Assembly
  • 6 = RoHS 6/6
BittWare Feature Arria 10 Family
Program Flash via PCIe via USB
Configure FPGA From Flash via PCIe via USB
Configure FPGA Directly via USB
Reset FPGA via PCIe via USB ✓ ✓
Access FPGA Registers, Memory Spaces From User Applications via PCIe via USB ✓ ✓
Virtual PCIe Hot-Swap
On-board JTAG Pod
Factory Backup Image with PCIe
Multiple User Images in Flash
Serial Number via PCIe via USB ✓ ✓
MAC Addresses For Each Network Interface via PCIe via USB ✓ ✓
BMC Voltage, Current, Temperature Sensors via PCIe via USB ✓ ✓
BMC Clock Re-programming via PCIe via USB
BMC FPGA Core Voltage Override via PCIe via USB
Upgrade BMC Firmware via PCIe via USB ✗ ✓
Documentation Quick-start Guide User’s Manual How-to Index BMC User’s Guide ✓ ✓ ✓ ✓
Examples PCIe DMA 10G Ethernet DDR4 Memory BMC Host (without using BittWare drivers) ✓ ✓ ✓ ✓