Intel Arria V GZ FPGA

The 28nm Arria V family of FPGAs deliver optimal performance, power, and cost efficiency for mid-range applications. The Arria V GZ variant, which is featured on the A5PS, offers the highest bandwidth of the Arria V FPGAs. The Arria V GZ provides Gen3 PCIe x8 via a hard IP block and features 16 full-duplex transceivers with data rates up to 12.5 Gbps, and up to 450K equivalent LEs.

I/O Interfaces

The A5PS provides a variety of interfaces for high-speed serial I/O as well as debug support. Two SFP+ cages are available on the front panel, each supporting a 10GigE channel using optical transceivers as well as passive copper cabling up to 8 meters.

The Gen3 x8 PCIe interface provides 8 SerDes lanes to the Arria V GZ FPGA. A USB 2.0 interface and an optional JTAG connector are available for debug and programming support.

Timestamping and Synchronization

The board supports timestamping and synchronization with optional SMA connectors on the front panel for a 1 PPS and reference clock input.* A tunable, high accuracy, temperature compensated oscillator (TCXO) and a programmable clock synthesizer (Si5338) provide sophisticated timing and clocking options. IP is also available for IEEE 1588 Precision Time Protocol (PTP).


The A5PS features an extremely flexible memory configuration, with a SODIMM site that supports DDR3 SDRAM, RLDRAM3, and QDRII+. Memory card options include the following: up to 8 GBytes of DDR3 with optional error-correcting codes (ECC); up to 36 MBytes QDRII+ (2 banks x18); or up to 512 MBytes RLDRAM3 (2 banks x18). Additional on-board memory includes flash memory for storing multiple FPGA images. An on-board PROM provides access to the board’s MAC ID.

Board Management Controller

Boards in BittWare’s A5 family feature an advanced system monitoring subsystem, similar to those typically found on today’s server platforms. At the heart of the board’s monitoring system lies a Board Management Controller (BMC), which accepts Intelligent Platform Management Interface (IPMI) messaging protocol commands. The BMC provides a wealth of features, including control of power and resets, monitoring of board sensors, FPGA boot loader, voltage overrides, configuration of programmable clocks, access to I2C bus components, field upgrades, and IPMI messaging. Access to the BMC is via PCIe or USB. BittWare’s BittWorks II Toolkit also provides utilities and libraries for communicating with the BMC components at a higher, more abstract level, allowing developers to remotely monitor the health of the board.

BwMonitor in the BittWorks II Toolkit provides a view into the baseboard management capabilities of your BittWare hardware.

Development Tools

BittWorks II Toolkit

BittWare offers complete software support for the A5PS with its BittWorks II software tools. Designed to make developing and debugging applications for BittWare’s boards easy and efficient, the Toolkit is a collection of libraries and applications that provides the glue between the host application and the hardware. A variety of features allow developers to take full advantage of the Arria V GZ FPGA capabilities on the BittWare board, including FPGA control via PCIe, Flash programming, custom ISR scripts, and convenient control of FPGA loads. The Toolkit supports 32-bit, and 64-bit Windows and Linux platforms and can connect to the board via PCIe or USB, providing a common API no matter the connection method.

* Requires full-height front panel

BittWare Firmware and Network Solutions Partners

BittWare offers firmware for the Arria V GZ FPGA on the A5 family PCIe boards, targeted specifically for networking applications. BittWare’s FPGA framework provides a solid base for your application, including the following:

  • 10GigE MAC
  • PCIe multi-channel DMA engines
  • DDR3 SDRAM and QDRII/II+ controllers

BittWare has also partnered with several companies to offer solutions for financial acceleration:

  • Algo-Logic: Market feed handler and low latency gateway libraries
  • Argon Design: Design services specializing in multimedia and FPGA-based high performance trading
  • Enyx: UOE, TOE, book building IP, order management IP, Market Feed Handler
  • Fraunhofer HHI: 10 GigE TCP & UDP Offload engines, 10GigE MACS and custom services
  • InDeLabs: Market Data Feed Handler and custom services
  • Intilop: Ultra low latency TOE, UOE, and MAC
  • LeWiz: Ultra low latency, multi-session TOE IP cores
  • Network Allies: IBM and Intel server computing systems
  • PLDA: Low latency TCP/IP offload engine, UDP and PCIe IP cores
  • PolyBus: Infiniband link layer and transport layer
  • Tamba Networks: Ultra low latency Ethernet and Interlaken cores


Board Specifications


  • Intel® Arria® V GZ FPGA
  • Up to 16 full-duplex, high-performance, multi-gigabit SerDes transceivers @ up to 12.5 GHz
  • Up to 450K logic elements available
  • Up to 34 Mb of embedded memory
  • 1.6 Gbps LVDS performance
  • Up to 2278 18×18 multipliers

On-Board Memory

  • Flash memory for booting FPGA

Optional SODIMM

  • DDR3: x72 w/ECC
    • Up to 8 GB
  • RLDRAM3: 2x banks of x18
    • 2x (32 M x 18): 128 MB
    • 2x (64 M x 18): 256 MB
    • 2x (128 M x 18): 512 MB
  • QDRII+: 2x banks of x18
    • 2x (8 M x 18): 36 MB

PCIe Interface

  • x8 Gen1, Gen2, Gen3 direct to FPGA

USB Header

  • USB 2.0 interface for debug and programming FPGA and Flash

Timestamp and Synchronization (Optional)

  • Tunable high-accuracy TCXO
  • Programmable clock synthesizer (Si5338)
  • 2 front panel SMA connectors*
    • 1 PPS input
    • Reference clock input

SFP+ Cages

  • 2 SFP+ cages on front panel connected to FPGA via 2 SerDes
  • Each supports 10GigE

Baseboard Management Controller

  • Voltage, current, temperature monitoring
  • Power sequencing and reset
  • Field upgrades
  • FPGA configuration and control
  • Clock configuration
  • I2C bus access
  • USB 2.0 access
  • Voltage overrides


  • Half-height, half-length (low profile) PCIe slot card

Development Tools

System Development

  • BittWorks II Toolkit – host, command, and debug tools for BittWare hardware; source code porting kit also available

FPGA Development

  • FPGA Development Kit
    • Physical interface components
    • Board, I/O, and timing constraints
    • Example Quartus projects
    • Software components and drivers
  • Intel Tools
    • Quartus II software

* Requires full-height front panel


RW Ruggedization
0U = Commercial (0C to 50C)*
AAAAAAAA Arria V Family, HardIP, and Size
GZME12C3 = Arria V GZME12C3*
GZME32C3 = Arria V GZME32C3 †
GZME52C3 = Arria V GZME52C3 †
GZME72C3 = Arria V GZME72C3
00 = None
99 = No socket †
D3 = DDR3 8GB x72*
Q2 = QDRII+ 36MB 2×18
R3 = RLDRAM3 512MB 2×18 †
C Oscillator
N = None
A = Adjustable TCXO
D Timing
0 = Not installed
X = On-board circuits only*
S = Front panel SMA connectors
E Misc. Configuration
1 = Default
F Environmental Assembly
6 = RoHS 6/6*
0 = Not Installed*
1 = Installed
2 = 2 SFP cages installed

* Default
† Contact BittWare for availability