Based on Altera’s Stratix IV GX FPGA, BittWare’s 4S-XMC (4SXM) is a single-width XMC, designed to provide powerful FPGA processing and high-speed serial I/O capabilities to VME, VXS, VPX, cPCI, AdvancedTCA, or PCI Express carrier boards. The 4SXM features a high-density, low-power Altera Stratix IV GX FPGA, which was designed specifically for serial I/O-based applications and is PCI SIG compliant for PCI Express Gen1 and Gen2. Four small form-factor pluggable (SFP) compact optical transceivers are available on the front panel. Eight multi-gigabit serial lanes supporting PCI Express, Serial RapidIO, and 10 GigE are available via the board’s rear panel as well as 44 general purpose digital I/O signals. The 4SXM also provides QDRII+ and Flash.
The 4SXM provides four SFP transceivers on the front panel with each transceiver providing support for virtually any serial communication standard, including: Fibre Channel, Gigabit Ethernet, SONET, CPRI, and OBSAI. The four SFP SerDes channels are connected directly to the Stratix IV GX FPGA. A 28-bit SFP control bus is also available to the Stratix IV GX.
The Altera Stratix IV GX was specifically designed for serial I/O-based applications requiring high-density, reconfigurable logic. The Stratix IV GX provides full-duplex, multi-gigabit transceivers, supporting PCI Express (Rev 1.0/2.0), 10 GigE, GigE, Serial RapidIO (Rev 1.0/2.0), and SerialLite II standards, as well as many others.
The 4SXM is compatible with BittWare’s GTV6 or any other standard VME, VXS, VPX, CompactPCI, AdvancedTCA, or PCI Express carrier board equipped with an XMC interface. The board complies with the VITA 42.0 XMC standard, the VITA 42.2 Serial RapidIO standard, and the VITA 42.3 XMC PCI Express Protocol standard. The primary XMC connector (J15) provides 8 SerDes lanes directly to the Stratix IV GX, while XMC J14 provides 44 general-purpose digital I/O signals to the FPGA.
Three reference oscillators are available on the 4SXM. The standard set includes 106.25 MHz for Fibre Channel, 100 MHz for PCI Express, and 156.25 MHz for Serial RapidIO or 10 GigE.
* SerDes max speed and protocol support may be FPGA speed grade dependent.
Figure 3: 4SXM System Block Diagram
0U = Commercial (0C to 50 C)*
11 = Altera Stratix IV GX 110*
18 = Altera Stratix IV GX 180
23 = Altera Stratix IV GX 230
29 = Altera Stratix IV GX 290
36 = Altera Stratix IV GX 360
|BB||FPGA Temperature Range & Speed Grade
C2 = Commercial / Speed Grade 2
C3 = Commercial / Speed Grade 3
C4 = Commercial / Speed Grade 4*
I3 = Industrial / Speed Grade 3
I4 = Industrial / Speed Grade 4)
6 = 128 MB
0 = None
1 = 9 MB QDRII+
2 = 9 MB QDRII *
0 = Standard (100, 106.25, 156.25 MHz)
0 = None
4 = 4 cages
0 = Not populated
1 = Populated *
00 = No transceivers
B = Blank
P = PCIe
S = SRIO
X = XAUI
6 = RoHS 6/6*