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S5-PCIe-HQ

Altera Stratix V GX/GS FPGA

The Altera Stratix V FPGA is optimized for high-performance, high-bandwidth applications with integrated transceivers supporting backplanes and optical modules. It supports 1.6 Tbps of serial switching capability and up to 3,926 18 x 18 variable precision multipliers. The Stratix V also provides PCI Express x8 via a hard IP block and supports configuration over PCI Express using the existing PCI Express link in your application. For additional flexibility, the Stratix V supports partial core reconfiguration on-the-fly while other portions of the design are running. The FPGA is supported by BittWare’s FPGA Development Kit, which provides board support IP and integration.

I/O Interfaces

The S5PH-Q provides a variety of interfaces for high-speed serial I/O as well as debug support. Two QSFP+ cages are available on the front panel, each supporting 40GigE or four 10GigE channels. The QSFP+ SerDes channels are connected directly to the Stratix V FPGA, thus removing the latency of external PHYs. The QSFP+ cages can optionally be adapted for SFP+.

Two SerDes lanes are available via two SATA connectors to connect external storage devices or provide direct board-to-board communication. The x8 PCIe interface provides 8 SerDes lanes to the Stratix V FPGA. USB 2.0, RS-232, and JTAG interfaces are available for debug and programming support. The board also supports timestamping with provision for a 1 PPS and reference clock input as well as RS-232 for connection to GPS or other time sources.

Memory

Several on-board memory banks are available to the Stratix V FPGA. Memory includes up to 16 GBytes of DDR3 SDRAM (two 64-bit banks) and up to 72 MBytes QDRII/II+ (four 18-bit banks). The S5PH-Q also provides flash memory for storing multiple FPGA images.

Board Management Controller

BittWare’s S5 boards feature an advanced system monitoring subsystem, similar to those typically found on today’s server platforms. At the heart of the board’s monitoring system lies a Board Management Controller (BMC), which accepts Intelligent Platform Management Interface (IPMI) messaging protocol commands. The BMC provides a wealth of features, including control of power and resets, monitoring of board sensors, FPGA boot loader, voltage overrides, configuration of programmable clocks, access to I2C bus components, field upgrades, and IPMI messaging. Access to the BMC is via PCIe, USB, or serial port. BittWare’s BittWorks II Toolkit also provides utilities and libraries for communicating with the BMC components at a higher, more abstract level, allowing developers to remotely monitor the health of the board.

BwMonitor in the BittWorks II Toolkit provides a view into the board management capabilities of your BittWare hardware.

Development Tools

BittWorks II Toolkit

BittWare offers complete software support for the S5PH-Q with its BittWorks II software tools. Designed to make developing and debugging applications for BittWare’s boards easy and efficient, the Toolkit is a collection of libraries and applications that provides the glue between the host application and the hardware. A variety of features allow developers to take full advantage of the Stratix V FPGA capabilities on the BittWare board, including FPGA control via PCIe, Flash programming, custom ISR scripts, and convenient control of FPGA loads. The Toolkit supports 32-bit, and 64-bit Windows and Linux platforms and can connect to the board via PCIe, Ethernet, or USB, providing a common API no matter the connection method.

FPGA Development Kit

BittWare’s FPGA Development Kit (FDK) provides FPGA board support IP and integration for BittWare’s Altera FPGA-based COTS boards. The FDK includes FPGA components that provide preconfigured physical interfaces, infrastructure, and examples, drastically cutting development time and easily integrating into existing FPGA development environments.

Working example projects are available for each board which illustrate how to move data between the board’s different interfaces. Supported interfaces include DDR3, DDR2, QDR2/+, PCIe, 10GigE, LVDS, SerDes, and Double Data Rate I/O. All example projects are available on BittWare’s Developer Site.

BittWare Firmware and Financial Solutions Partners

BittWare offers firmware for the Stratix V FPGA on the S5 family PCIe boards, targeted specifically for high frequency trading applications. BittWare’s FPGA Development Kit provides a solid base for your financial application, including the following:

  • 10GigE MAC
  • PCIe multi-channel DMA engines
  • DDR3 SDRAM and QDRII/II+ controllers

BittWare has also partnered with several companies to offer solutions for financial acceleration:

  • Algo-Logic: Market feed handler and low latency gateway libraries
  • Argon Design: Design services specializing in multimedia and FPGA-based high performance trading
  • Atomic Rules: Custom IP development, example UDP, precision timestamping, PCIe, networking
  • Enyx: UOE, TOE, book building IP, order management IP, Market Feed Handler
  • InDeLabs: Market Data Feed Handler and custom services
  • Intilop: Ultra low latency TOE, UOE, and MAC
  • LeWiz: Ultra low latency, multi-session TOE IP cores
  • PolyBus: Infiniband link layer and transport layer
  • Tamba Networks: Ultra low latency Ethernet and Interlaken cores

Specifications

Board Specifications

FPGA

  • Altera® Stratix® V GX/GS FPGA
  • 20 full-duplex, high-performance, multi-gigabit SerDes transceivers @ up to 14.1 GHz
  • Up to 952,000 logic elements (LEs) available
  • Up to 62 Mb of embedded memory
  • 1.4 Gbps LVDS performance
  • Up to 3,926 18×18 variable-precision multipliers
  • Embedded HardCopy Blocks

Memory

  • Two banks of up to 8 GBytes DDR3 SDRAM (x64)
  • Four banks of up to 18 MBytes QDRII+ (x18)
  • 128 MBytes of Flash memory for booting FPGA

PCIe Interface

  • x8 Gen1, Gen2, Gen3 direct to FPGA

USB Header

  • USB 2.0 interface for debug and programming FPGA and Flash

Timestamp Header

  • 1 PPS input
  • Reference clock input
  • RS-232

Debug Utility Header

  • RS-232 port to Stratix V
  • JTAG debug interface to Stratix V

QSFP+ Cages

  • 2 QSFP+ cages on front panel connected directly to FPGA via 8 SerDes (no external PHY)
  • Each supports 40 GigE or four 10 GigE interfaces
  • Can be optionally adapted for use as SFP+

Serial ATA

  • 2 SATA connectors, connected to FPGA

Board Management Controller

  • Voltage, current, temperature monitoring
  • Field upgrades
  • FPGA configuration and control
  • Clock configuration
  • I2C bus access
  • USB 2.0 and JTAG access
  • Voltage overrides

Size

  • Half-length, standard-height PCIe slot card
  • 168mm x 111.15mm
  • Max. component height: 14.47mm

Development Tools

System Development

  • BittWorks II Toolkit – host, command, and debug tools for BittWare hardware; source code porting kit also available

FPGA Development Kit

  • Physical interface components
  • Board, I/O, and timing constraints
  • Example Quartus projects
  • Software components and drivers

FPGA Development

  • Altera Quartus® II software

Accessory Boards

  • BittWare BWBO breakout board for JTAG and RS-232 access

Ordering

S5PHQ-RW-AAAAABCC-DEFGHIJKLM-0-O0QRS
RW Ruggedization 0U = Commercial (0C to 50C)*
AAAAA Stratix V Family, HardIP, and Size GXEA3 = Stratix V GXEA3 GXEA4 = Stratix V GXEA4 GXEA5 = Stratix V GXEA5 GXEA7 = Stratix V GXEA7* GXEA9 = Stratix V GXEA9† GXEAB = Stratix V GXEAB† GSMD4 = Stratix V GSMD4 GSMD5 = Stratix V GSMD5 GSED6 = Stratix V GSED6† GSED8 = Stratix V GSED8†
B Stratix V GXB Speed 1 = 14.1 Gbps 2 = 12.5 Gbps*‡ 3 = 8.5 Gbps
CC Stratix V Temp/Speed C1= Commercial Temperature Range, Speed Grade 1 C2= Commercial Temperature Range, Speed Grade 2* C3= Commercial Temperature Range, Speed Grade 3
D DDR3 Bank A 0 = None A = 2GB B = 4GB* C = 8GB
E DDR3 Bank B 0 = None A = 2GB B = 4GB* C = 8GB
F QDR II Bank A 0 = None 2 = 9MB 3 = 18MB*
G QDR II Bank A Type & Speed 0 = None 3 = QDR2 333MHz D = QDR2+ 550MHz*
H QDR II Bank B 0 = None 2 = 9MB 3 = 18MB*
I QDR II Bank B Type & Speed 0 = None 3 = QDR2 333MHz D = QDR2+ 550MHz*
J QDR II Bank C 0 = None 2 = 9MB 3 = 18MB*
K QDR II Bank C Type & Speed 0 = None 3 = QDR2 333MHz D = QDR2+ 550MHz*
L QDR II Bank D 0 = None 2 = 9MB 3 = 18MB*
M QDR II Bank D Type & Speed 0 = None 3 = QDR2 333MHz D = QDR2+ 550MHz
O Oscillator S = Standard*
Q Heatsink A = Board Fansink Single Slot B = FPGA Fansink* C = FPGA Fansink Dual Slot D = FPGA Heatsink Dual Slot E = FPGA Heat sink single slot
R Misc. Configuration 0 = Standard
S Envelope Assembly 6 = RoHS 6/6* P = SnPb assembly
*Default † Contact BittWare for availability. ‡ On GXEAB devices, the Stratix V GXB speed is 11.2 Gbps.

S5PE-DS PCIe FPGA Board

Altera Stratix V GX/GS FPGA

The Altera Stratix V FPGA is optimized for high-performance, high-bandwidth applications with integrated transceivers (up to 14.1 Gbps) supporting backplanes and optical modules. It supports 1.6 Tbps of serial switching capability and up to 3,926 18 x 18 variable precision multipliers. The Stratix V also provides PCI Express x8 via a hard IP block and supports configuration by PCI Express using the existing PCI Express link in your application. For additional flexibility, the Stratix V supports transceiver and core reconfiguration on-the-fly while other portions of the design are running. The two FPGAs are interconnected via 8 SerDes transceivers and 36 single-ended signals. The FPGAs are supported by BittWare’s FPGA Development Kit, which provides FPGA board support IP and integration.

I/O Interfaces

The S5PE-DS provides a variety of interfaces for high-speed serial I/O as well as debug support. Four QSFP+ cages are available on the front panel, each supporting 40GigE, 4 10GigE channels, or QDR/FDR InfiniBand. The QSFP+ SerDes channels are connected directly to the Stratix V FPGAs, thus removing the latency of external PHYs. Eight SATA connectors are provided to connect external storage devices with the FPGAs via SerDes lanes. The Gen3 x16 PCIe interface is supported by a PCIe switch (PLX PEX8733), which provides on-chip DMA engines as well as a Gen3 x8 connection to each FPGA. USB 2.0, RS-232, and JTAG interfaces are available for debug and programming support. The board also supports timestamping with provision for a 1 PPS and reference clock input as well as RS-232 for connection to GPS or other time sources.

Memory and SODIMM Options

The S5PE-DS features an extremely flexible memory configuration, with 8 SODIMM sites (4 per FPGA) supporting DDR3 SDRAM, RLDRAM3, and QDRII+*. SODIMMs are available in the following configurations: up to 8 GBytes DDR3 with optional error-correcting codes (ECC); up to 36 MBytes QDRII+ (2 banks x18); or up to 512 MBytes RLDRAM3 (2 banks x18). The board also provides Flash memory for storing multiple FPGA images.

Board Management Controller

BittWare’s S5 boards feature an advanced system monitoring subsystem, similar to those typically found on today’s server platforms. At the heart of the board’s monitoring system lies a Board Management Controller (BMC), which accepts Intelligent Platform Management Interface (IPMI) messaging protocol commands. The BMC provides a wealth of features, including control of power and resets, monitoring of board sensors, FPGA boot loader, voltage overrides, configuration of programmable clocks, access to I2C bus components, field upgrades, and IPMI messaging. Access to the BMC is via PCIe, USB, or serial port. BittWare’s BittWorks II Toolkit also provides utilities and libraries for communicating with the BMC components at a higher, more abstract level, allowing developers to remotely monitor the health of the board. BwMonitor in the BittWorks II Toolkit provides a view into the board management capabilities of your BittWare hardware.

Development Tools

BittWorks II Toolkit

BittWare offers complete software support for the S5PE-DS with its BittWorks II software tools. Designed to make developing and debugging applications for BittWare’s boards easy and efficient, the Toolkit is a collection of libraries and applications that provides the glue between the host application and the hardware. A variety of features allow developers to take full advantage of the Stratix V FPGA capabilities on the BittWare board, including FPGA control via PCIe, Flash programming, custom ISR scripts, and convenient control of FPGA loads. The Toolkit supports 32-bit, and 64-bit Windows and Linux platforms and can connect to the board via PCIe, Ethernet, or USB, providing a common API no matter the connection method.

FPGA Development Kit

BittWare’s FPGA Development Kit (FDK) provides FPGA board support IP and integration for BittWare’s Altera FPGA-based COTS boards. The FDK includes FPGA components that provide preconfigured physical interfaces, infrastructure, and examples, drastically cutting development time and easily integrating into existing FPGA development environments. Working example projects are available for each board which illustrate how to move data between the board’s different interfaces. Supported interfaces include DDR3, DDR2, QDR2/+, PCIe, 10GigE, LVDS, SerDes, and Double Data Rate I/O. All example projects are available on BittWare’s Developer Site. *QDRII+ is available on up to two SODIMM sites per FPGA. All other SODIMM options are supported on up to four sites per FPGA.

BittWare Firmware and Financial Solutions Partners

BittWare offers firmware for the Stratix V FPGA on the S5 family PCIe boards, targeted specifically for high frequency trading applications. BittWare’s FPGA Development Kit provides a solid base for your financial application, including the following:
  • 10GigE MAC
  • PCIe multi-channel DMA engines
  • DDR3 SDRAM and QDRII/II+ controllers
BittWare has also partnered with several companies to offer solutions for financial acceleration:
  • Algo-Logic: Market feed handler and low latency gateway libraries
  • Argon Design: Design services specializing in multimedia and FPGA-based high performance trading
  • Atomic Rules: Custom IP development, example UDP, precision timestamping, PCIe, networking
  • Enyx: UOE, TOE, book building IP, order management IP, Market Feed Handler
  • InDeLabs: Market Data Feed Handler and custom services
  • Intilop: Ultra low latency TOE, UOE, and MAC
  • LeWiz: Ultra low latency, multi-session TOE IP cores
  • PolyBus: Infiniband link layer and transport layer
  • Tamba Networks: Ultra low latency Ethernet and Interlaken cores

FPGAs

  • 2 Altera® Stratix® V GX/GS FPGAs
  • 28 full-duplex, high-performance, multi-gigabit SerDes transceivers @ up to 14.1 Gbps (per FPGA)
  • Up to 952,000 logic elements (LEs) per FPGA
  • Up to 62 Mb of embedded memory per FPGA
  • 1.4 Gbps LVDS performance
  • Up to 3,926 18×18 variable-precision multipliers per FPGA
  • Embedded HardCopy Blocks

Memory

  • 4 SODIMM sites per FPGA: DDR3 SDRAM, RLDRAM3, or QDRII+ options
  • 256 MBytes of Flash memory for booting FPGA

PCIe Interface

  • PLX PEX8733 PCIe switch with on-chip DMA engines
  • x16 Gen1, Gen2, Gen3 to host
  • x8 Gen 1, Gen2, Gen 3 to each FPGA

USB Header

  • USB 2.0 interface for debug and programming FPGAs and Flash

Timestamp Header

  • 1 PPS input
  • Reference clock input
  • RS-232

Debug Utility Header

  • RS-232 port to Stratix V
  • JTAG debug interface to Stratix V

QSFP+ Cages

  • 4 QSFP+ cages on front panel connected directly to FPGAs via 16 SerDes (no external PHY)
  • Each QSFP+ supports 40GigE, 4 10GigE, or QDR/FDR InfiniBand interfaces

Serial ATA

  • 8 SATA connectors, connected to FPGAs

Board Management Controller

  • Voltage, current, temperature monitoring
  • Power sequencing and reset
  • Field upgrades
  • FPGA configuration and control
  • Clock configuration
  • I2C bus access
  • USB 2.0 and JTAG access
  • Voltage overrides

Size

  • Full-length, standard-height, dual-slot PCIe x16 card
  • 312mm x 111.15mm
  • Max. component height: 34mm

Development Tools

System Development

  • BittWorks II Toolkit – host, command, and debug tools for BittWare hardware; source code porting kit also available

FPGA Development Kit

  • Physical interface components
  • Board, I/O, and timing constraints
  • Example Quartus projects
  • Software components and drivers

FPGA Development

  • Altera Quartus® II software

Accessory Boards

  • BittWare BWBO breakout board for debug
S5PEDS-RW-AAAAABCC-DDEEFFGG-HHHHHIJJ-KKLLMMNN-OPQRS
RW Ruggedization 0U = Commercial (0C to 50C)*
AAAAA Stratix V A Family, HardIP, and Size GXEA7 = Stratix V GXEA7† GXEAB = Stratix V GXEAB* GSMD5 = Stratix V GSMD5† GSED8 = Stratix V GSED8*
B Stratix V A GXB Speed 1 = 14.1 Gbps 2 = 12.5 Gbps*‡ 3 = 8.5 Gbps
CC Stratix V A Temp/Speed C1= Commercial Temperature Range, Speed Grade 1 C2= Commercial Temperature Range, Speed Grade 2* C3= Commercial Temperature Range, Speed Grade 3
DD Cluster A SODIMM 1 00 = None D3 = DDR3 8GB x72* Q2 = QDRII+ 36MB 2×18 R2 = RLDRAM3 256MB 2×18 † R3 = RLDRAM3 512MB 2×18 †
EE Cluster A SODIMM 2 See options for “Cluster A SODIMM 1” (DD)
FF Cluster A SODIMM 3 00 = None D3 = DDR3 8GB x72* R2 = RLDRAM3 256MB 2×18 † R3 = RLDRAM3 512MB 2×18 †
GG Cluster A SODIMM 4 See options for “Cluster A SODIMM 3” (FF)
HHHHH Stratix V B Family, HardIP, and Size See options for Stratix V A (AAAAA)
I Stratix V B GXB Speed 1 = 14.1 Gbps 2 = 12.5 Gbps*‡ 3 = 8.5 Gbps
JJ Stratix V B Temp/Speed C1= Commercial Temperature Range, Speed Grade 1 C2= Commercial Temperature Range, Speed Grade 2* C3= Commercial Temperature Range, Speed Grade 3
KK Cluster B SODIMM 1 00 = None D3 = DDR3 8GB x72* Q2 = QDRII+ 36MB 2×18 R2 = RLDRAM3 256MB 2×18 † R3 = RLDRAM3 512MB 2×18 †
LL Cluster B SODIMM 2 See options for “Cluster B SODIMM 1” (KK)
MM Cluster B SODIMM 3 00 = None D3 = DDR3 8GB x72* R2 = RLDRAM3 256MB 2×18 † R3 = RLDRAM3 512MB 2×18 †
NN Cluster B SODIMM 4 See options for “Cluster B SODIMM 3” (MM)
O Misc. Configuration 0 = Standard
P Oscillator S = Standard*
Q Heatsink B = FPGA Fansink* E = FPGA Heatsink
R Power Supply R – Right-Angle Connector* V – Vertical Connector
S Envelope Assembly 6 = RoHS 6/6*

SODIMM Compatibility Table

SODIMM Site 1 Site 2 Site 3 Site 4
DDR3 Yes Yes Yes Yes
QDRII+ Yes** Yes** No
RLDRAM Yes Yes Yes Yes

S5PE-F PCIe FPGA Board

Intel Stratix V GX/GS FPGA

The Intel Stratix V FPGA is optimized for high-performance, high-bandwidth applications with integrated transceivers (up to 14.1 Gbps) supporting backplanes and optical modules. It supports 1.6 Tbps of serial switching capability and up to 3,926 18 x 18 variable precision multipliers. The Stratix V also provides PCI Express x8 via a hard IP block and supports configuration by PCI Express using the existing PCI Express link in your application. For additional flexibility, the Stratix V supports transceiver and core reconfiguration on-the-fly while other portions of the design are running. The FPGA is supported by BittWare’s FPGA Development Kit, which provides board support IP and integration.

VITA 57 FMC and Expansion Sites for Processing and I/O

The S5PE-F features an FMC (FPGA Mezzanine Card) site, which provides high-performance SerDes and LVDS, along with clocks, I2C, and JTAG connected to the Stratix V. The site is based on the VITA 57 mezzanine standard for FPGA I/O, enabling designers to customize the S5PE-F to their individual needs with optional FMC I/O boards. A variety of I/O or processor FMCs are available integrated with the S5PE-F.

An additional expansion site provides 10 SerDes and general-purpose I/O to the Stratix V. The site can be used for board-to-board communication, general-purpose I/O, or additional optical links.

I/O Interfaces

The S5PE-F provides a variety of interfaces for high-speed serial I/O as well as debug support. Four SerDes lanes are available via four SATA connectors to connect external storage devices with the FPGA or provide direct board-to-board communication. The x8 PCIe interface provides 8 SerDes lanes to the Stratix V FPGA. USB 2.0, RS-232, and JTAG interfaces are available for debug and programming support. The board also supports timestamping with provision for a 1 PPS and reference clock input as well as RS-232 for connection to GPS or other time sources.

Memory and SODIMM Options

The S5PE-F features an extremely flexible memory configuration, with two SODIMM sites that support DDR3 SDRAM, RLDRAM3, and QDRII+. Memory card options include the following: up to 8 GBytes of DDR3 with optional error-correcting codes (ECC); up to 36 MBytes QDRII+ (2 banks x18); or up to 512 MBytes RLDRAM3 (2 banks x18). RLDRAM3 is a high-performance memory targeted for systems requiring high bandwidth and low latency. The board also provides Flash memory for storing multiple FPGA images.

Board Management Controller

BittWare’s S5 boards feature an advanced system monitoring subsystem, similar to those typically found on today’s server platforms. At the heart of the board’s monitoring system lies a Board Management Controller (BMC), which accepts Intelligent Platform Management Interface (IPMI) messaging protocol commands. The BMC provides a wealth of features, including control of power and resets, monitoring of board sensors, FPGA boot loader, voltage overrides, configuration of programmable clocks, access to I2C bus components, field upgrades, and IPMI messaging. Access to the BMC is via PCIe, USB, or serial port. BittWare’s BittWorks II Toolkit also provides utilities and libraries for communicating with the BMC components at a higher, more abstract level, allowing developers to remotely monitor the health of the board.

BwMonitor in the BittWorks II Toolkit provides a view into the board management capabilities of your BittWare hardware.

Development Tools

BittWorks II Toolkit

BittWare offers complete software support for the S5PE-F with its BittWorks II software tools. Designed to make developing and debugging applications for BittWare’s boards easy and efficient, the Toolkit is a collection of libraries and applications that provides the glue between the host application and the hardware. A variety of features allow developers to take full advantage of the Stratix V FPGA capabilities on the BittWare board, including FPGA control via PCIe, Flash programming, custom ISR scripts, and convenient control of FPGA loads. The Toolkit supports 32-bit, and 64-bit Windows and Linux platforms and can connect to the board via PCIe, Ethernet, or USB, providing a common API no matter the connection method.

FPGA Development Kit

BittWare’s FPGA Development Kit (FDK) provides FPGA board support IP and integration for BittWare’s Intel FPGA-based COTS boards. The FDK includes FPGA components that provide preconfigured physical interfaces, infrastructure, and examples, drastically cutting development time and easily integrating into existing FPGA development environments.

Working example projects are available for each board which illustrate how to move data between the board’s different interfaces. Supported interfaces include DDR3, DDR2, QDR2/+, PCIe, 10GigE, LVDS, SerDes, and Double Data Rate I/O. All example projects are available on BittWare’s Developer Site.

FMC I/O Options

FPGA COTS Hardware

BittWare Firmware and Financial Solutions Partners

BittWare offers firmware for the Stratix V FPGA on the S5 family PCIe boards, targeted specifically for high frequency trading applications. BittWare’s FPGA Development Kit provides a solid base for your financial application, including the following:

  • 10GigE MAC
  • PCIe multi-channel DMA engines
  • DDR3 SDRAM and QDRII/II+ controllers

BittWare has also partnered with several companies to offer solutions for financial acceleration:

  • Algo-Logic: Market feed handler and low latency gateway libraries
  • Argon Design: Design services specializing in multimedia and FPGA-based high performance trading
  • Atomic Rules: Custom IP development, example UDP, precision timestamping, PCIe, networking
  • Enyx: UOE, TOE, book building IP, order management IP, Market Feed Handler
  • InDeLabs: Market Data Feed Handler and custom services
  • Intilop: Ultra low latency TOE, UOE, and MAC
  • LeWiz: Ultra low latency, multi-session TOE IP cores
  • PolyBus: Infiniband link layer and transport layer
  • Tamba Networks: Ultra low latency Ethernet and Interlaken cores

Board Specifications

VITA 57 FMC Site (optional)

  • Full High Pin Count support
  • 10x high-performance SerDes
  • 80 bi-directional LVDS
  • Clocks, I2C, and JTAG

FPGA

  • Intel® Stratix® V GX/GS FPGA
  • 32 full-duplex, high-performance, multi-gigabit SerDes transceivers @ up to 14.1 Gbps
  • Up to 952,000 logic elements (LEs) available
  • Up to 62 Mb of embedded memory
  • 1.4 Gbps LVDS performance
  • Up to 3,926 18×18 variable-precision multipliers
  • Embedded HardCopy Blocks

Memory

  • 2 SODIMM sites supporting DDR3, RLDRAM3, or QDRII+
  • Up to 256 MBytes of Flash memory for booting FPGA

PCIe Interface

  • x8 Gen1, Gen2, Gen3 direct to FPGA

I/O and Debug Connectors

  • Serial ATA: 4 connectors direct to FPGA, 6 Gbps
  • Timestamp header: 1 PPS input, reference clock input, and RS-232
  • USB 2.0: for debug and programming FPGA and Flash
  • Debug Utility header: RS-232 and JTAG to Stratix V

Expansion Site

  • 10x high-performance SerDes
  • General-purpose I/O

Board Management Controller

  • Voltage, current, temperature monitoring
  • Power sequencing and reset
  • Field upgrades
  • FPGA configuration and control
  • Clock configuration
  • I2C bus access
  • USB 2.0 and JTAG access
  • Voltage overrides

Size

  • Full-length, standard-height PCIe slot card
  • x16 mechanical, x8 electrical

Optional SODIMMs*

DDR3: x72 w/ECC

  • Up to 8 GB per SODIMM (DDR3-1600)

RLDRAM3: 2x banks of x18

  • 2x (32 M x 18): 128 MB per SODIMM
  • 2x (64 M x 18): 256 MB per SODIMM
  • 2x (128M x 18): 512 MB per SODIMM

QDRII+: 2x banks of x18

  • 2x (4 MB x 18): 18 MB per SODIMM
  • 2x (8 MB x 18): 36 MB per SODIMM

Development Tools

System Development

  • BittWorks II Toolkit – host, command, and debug tools for BittWare hardware; source code porting kit also available

FPGA Development Kit

  • Physical interface components
  • Board, I/O, and timing constraints
  • Example Quartus projects
  • Software components and drivers

FPGA Development

  • Intel Quartus® II software

Accessory Boards

  • BittWare BWBO breakout board for JTAG and RS-232 access

* Combining two different SODIMM types on the S5PE-F places a restriction on using the full High Pin Count of the FMC site. If both SODIMM sites are populated with the same type of SODIMM, there is no restriction.

Ordering

S5PEF-RW-AAAAABCC-DDEE-FGH-IJK-L
RW Ruggedization
0U = Commercial (0C to 50C)*
AAAAA Stratix V Family, HardIP, and Size
GXEA3 = Stratix V GXEA3†
GXEA4 = Stratix V GXEA4†
GXEA5 = Stratix V GXEA5†
GXEA7 = Stratix V GXEA7†
GXEA9 = Stratix V GXEA9†
GXEAB = Stratix V GXEAB*
GSMD4 = Stratix V GSMD4†
GSMD5 = Stratix V GSMD5†
GSED6 = Stratix V GSED6†
GSED8 = Stratix V GSED8*
B Stratix V GXB Speed
1 = 14.1 Gbps
2 = 12.5 Gbps*‡
3 = 8.5 Gbps
CC Stratix V Temp/Speed
C1= Commercial Temperature Range, Speed Grade 1
C2= Commercial Temperature Range, Speed Grade 2*
C3= Commercial Temperature Range, Speed Grade 3
DD Cluster A SODIMM
00 = None
D1 = DDR3 2GB x72
D2 = DDR3 4GB x72
D3 = DDR3 8GB x72*
Q1 = QDRII+ 18MB 2×18
Q2 = QDRII+ 36MB 2×18
R1 = RLDRAM3 128MB 2×18 †
R2 = RLDRAM3 256MB 2×18 †
R3 = RLDRAM3 512MB 2×18 †
EE Cluster B SODIMM
00 = None
D1 = DDR3 2GB x72
D2 = DDR3 4GB x72
D3 = DDR3 8GB x72*
Q1 = QDRII+ 18MB 2×18
Q2 = QDRII+ 36MB 2×18
R1 = RLDRAM3 128MB 2×18 †
R2 = RLDRAM3 256MB 2×18 †
R3 = RLDRAM3 512MB 2×18 †
F Front Expansion Site
1 = FMC
G Rear Expansion Site
0 = Not installed
1 = Installed
H Oscillator
S = Standard
T = TCXO
I Heatsink
B = FPGA Fansink*
E = FPGA Heatsink
J Mechanical Options
1 = 1 slot standard
2 = 2 slot standard
K Misc. Configuration
0 = Standard
L Envelope Assembly
6 = RoHS 6/6*

* Default
† Contact BittWare for availability.
‡ On GXEAB devices, the Stratix V GXB speed is 11.2 Gbps.

S56X VPX FPGA Board

Intel Stratix V GX/GS FPGA

The Intel Stratix V FPGA is optimized for high-performance, high-bandwidth applications with integrated transceivers (up to 14.1 Gbps) supporting backplanes and optical modules. It supports 1.6 Tbps of serial switching capability and up to 3,926 18 x 18 variable precision multipliers. The Stratix V also provides PCI Express via a hard IP block and supports configuration by PCI Express using the existing PCI Express link in your application. For additional flexibility, the Stratix V supports transceiver and core reconfiguration on-the-fly while other portions of the design are running. TThe FPGA is supported by BittWare’s FPGA Development Kit, which provides board support IP and integration.

Learn about our Ruggedization Capabilities

I/O Interfaces

The S56X provides a variety of interfaces for high-speed serial I/O as well as debug support. The rear panel VPX interface includes GigE and 32 multi-gigabit transceiver channels to the Stratix V FPGAs. In addition, a Cyclone III FPGA is used to interface 48 LVDS and 20 GPIO from the VPX backplane to the Stratix V FPGAs. A utility header provides access to USB, RS-232, JTAG, and Ethernet interfaces for debug and programming support.

ARM Cortex-A8 Control Processor

An ARM Cortex-A8 control processor provides a complete control plane interface for the S56X, facilitating separate control and data planes, and greatly simplifying the development of data plane I/O and processing. This is implemented in a 800 MHz TI AM3871 ARM processor running Linux. The ARM runs BittWorks server for full remote access via the BittWorks II Toolkit.

Board Management Controller

BittWare’s S5 boards feature an advanced system monitoring subsystem, similar to those typically found on today’s server platforms. At the heart of the board’s monitoring system lies a Board Management Controller (BMC), which accepts Intelligent Platform Management Interface (IPMI) messaging protocol commands. The BMC provides a wealth of features, including control of power and resets, monitoring of board sensors, FPGA boot loader, voltage overrides, configuration of programmable clocks, access to I2C bus components, field upgrades, and IPMI messaging. Access to the BMC is via PCIe, USB, or serial port. BittWare’s BittWorks II Toolkit also provides utilities and libraries for communicating with the BMC components at a higher, more abstract level, allowing developers to remotely monitor the health of the board.

Development Tools

BittWorks II Toolkit

BittWare offers complete software support for the S56X with its BittWorks II software tools. Designed to make developing and debugging applications for BittWare’s boards easy and efficient, the Toolkit is a collection of libraries and applications that provides the glue between the host application and the hardware. A variety of features allow developers to take full advantage of the Stratix V FPGA capabilities on the BittWare board, including FPGA control via PCIe, Flash programming, custom ISR scripts, and convenient control of FPGA loads. The Toolkit supports 32-bit, and 64-bit Windows and Linux platforms and can connect to the board via PCIe, Ethernet, or USB, providing a common API no matter the connection method.

VITA 57 FMC Sites for Processing and I/O Expansion

The S56X features two FMC (FPGA Mezzanine Card) sites, which provide multi-gigabit transceivers and LVDS, along with clocks, I2C, JTAG, and reset connected to the Stratix V. The sites are based on the VITA 57 mezzanine standard for FPGA I/O, enabling designers to customize the S56X to their individual needs with optional FMC I/O boards.

FPGA Development Kit

BittWare’s FPGA DevKit provides FPGA board support IP and integration for BittWare’s Intel FPGA-based COTS boards. The FDK includes FPGA components that provide preconfigured physical interfaces, infrastructure, and examples, drastically cutting development time and easily integrating into existing FPGA development environments.

Working example projects are available for each board which illustrate how to move data between the board’s different interfaces. Supported interfaces include DDR3, DDR2, QDR2/+, PCIe, 10GigE, LVDS, SerDes, and Double Data Rate I/O. All example projects are available on BittWare’s Developer Site.

Specs

Board Architecture

VITA 57 FMC Sites

  • Two VITA 57 FMC sites
  • 8x multi-gigabit transceivers per site
  • 80 LVDS pairs per site
  • Clocks, I2C, JTAG, and reset

FPGAs

  • 2 Intel® Stratix® V GX/GS FPGAs
  • 48 full-duplex, multi-gigabit transceivers @ up to 14.1 GHz
  • Up to 952,000 logic elements per FPGA
  • Up to 62 Mb on-chip memory (per FPGA)
  • 1.4 Gbps LVDS performance
  • Up to 3,926 18×18 variable-precision multipliers (per FPGA)
  • Embedded HardCopy Blocks

External Memory

  • Four banks of up to 2 GByte DDR3 SDRAM configured as x64
  • Two 128 MByte banks of Flash memory for booting FPGA and ARM

ARM® Cortex™-A8 Control Processor

  • 800 MHz ARM® Cortex™-A8 processor (TI AM3871) running Linux
  • Control port interface to Stratix V FPGAs
  • GigE, PCIe, and SATA interfaces
  • Supports host- and Flash-based booting of Stratix V FPGAs
  • Runs BittWorks server for full remote access via the BittWorks II Toolkit

Rear Panel I/O

  • 4 GigE (2 1000BaseT and 2 1000BaseX)
  • 16 multi-gigabit transceivers from rear panel (VPX) to each Stratix V (32 total)
  • 48 LVDS pairs (24 Tx and 24 Rx) and 20 GPIO from VPX backplane to the Stratix V FPGAs via a Cyclone III FPGA

Debug I/O (Utility Header)

  • RS-232 ports to Stratix V and ARM
  • Ethernet interface (10/100)
  • JTAG debug interface to the Stratix V

Size

  • VPX 6U single slot

Board Management Controller

  • Voltage, current, temperature monitoring
  • Power sequencing and reset
  • Field upgrades
  • FPGA configuration and control
  • Clock configuration
  • I2C bus access
  • USB 2.0 and JTAG access
  • Voltage overrides

Development Tools

System Development

  • BittWorks II Toolkit – host, command, and debug tools for BittWare hardware
  • BittWorks II Porting Kit – source code and prebuilt ports for porting the BittWorks II Toolkit to other operating systems

FPGA Development Kit

  • Physical interface components
  • Board, I/O, and timing constraints
  • Example Quartus projects
  • Software components and drivers

FPGA Development

  • Intel Quartus® II software

Accessory Boards

  • BittWare BWBO breakout board for USB, JTAG, RS-232, and Ethernet access
  • BittWare ACC-S56X-BORT rear transition module with QSFP, SFP, RJ-45, JTAG, PCIe x1, SATA, and Ref Clk input

Ordering

S56X-RW-AAAAABCC-DE-0-GGGGGHII-JK-0-MN-OPQR-STUV-WX
RW Ruggedization
0U = Commercial (0C to 50C)*
AAAAA Cluster A S5 Family, HardIP, and Size
00000 = None
GXEA3 = Stratix V GXEA3
GXEA4 = Stratix V GXEA4
GXEA5 = Stratix V GXEA5
GXEA7 = Stratix V GXEA7*
GXEA9 = Stratix V GXEA9†
GXEAB = Stratix V GXEAB†
GSMD4 = Stratix V GSMD4
GSMD5 = Stratix V GSMD5
GSED6 = Stratix V GSED6†
GSED8 = Stratix V GSED8†
B Cluster A S5GXB Speed
1 = 14.1 Gbps
2 = 12.5 Gbps*‡
3 = 8.5 Gbps
CC Cluster A S5 Temp/Speed
00 = None
I3 = Industrial Temperature Range, Speed Grade 3
I4 = Industrial Temperature Range, Speed Grade 4*
D Cluster A DDR3 Bank A
0 = None
9 = 1GB
A = 2 GB*
E Cluster A DDR3 Bank B
0 = None
9 = 1GB
A = 2 GB*
GGGGG Cluster B S5 Family, HardIP, and Size
(See options for AAAAA)
H Cluster B S5GXB Speed
1 = 14.1 Gbps
2 = 12.5 Gbps*‡
3 = 8.5 Gbps
II Cluster B S5 Temp/Speed
00 = None
I3 = Industrial Temperature Range, Speed Grade 3
I4 = Industrial Temperature Range, Speed Grade 4*
J Cluster B DDR3 Bank A
0 = None
9 = 1GB
A = 2 GB*
K Cluster B DDR3 Bank B
0 = None
9 = 1GB
A = 2 GB*
M Rear Panel Analog Connectors
0 = Not Populated
1 = Populated*
N VPX I/O Configuration
1 = Standard
O ClusterA Reference Clock A Frequency
0 = 156.25MHz*
P Cluster B Reference Clock A Frequency
0 = 156.25MHz*
Q Reference Clock B Frequency
5 = 322.265625MHz*
R Reference Clock C Frequency
0 = 125 MHz*
S VPX Rear Panel Connectors
1 = Standard (P0 – P4 installed)*
T VPX Key Position 1
1 = 0 Degrees
2 = 45 Degrees
3 = 90 Degrees
7 = 270 Degrees
8 = 315 Degrees*
9 = Unkeyed
U VPX Key Position 2
1 = 0 Degrees
2 = 45 Degrees
3 = 90 Degrees
7 = 270 Degrees
8 = 315 Degrees
9 = Unkeyed*
V VPX Key Position 3
1 = 0 Degrees
2 = 45 Degrees
3 = 90 Degrees
7 = 270 Degrees
8 = 315 Degrees
9 = Unkeyed*
W Mechanical
1 = Standard Air Cooled Panel*
2 = 1” Pitch Air Cooled Panel
3 = Standard Conduction Cooled Frame
4 = 1” Pitch Conduction Cooled Frame
X Environmental Assembly
P = SnPb assembly*
* Default † Contact BittWare for availability. ‡ On GXEAB devices, the Stratix V GXB speed is 11.2 Gbps.

OpenCL Developer’s Bundle

BittWare Hardware

A10PL4 PCIe Board

BittWare’s A10PL4 is a Gen3 x8 low-profile PCIe card based on the Arria 10 FPGA, ideal for a wide range of applications, including network processing and security, compute and storage, instrumentation, broadcast, and SigInt. The board offers 8 GBytes DDR4, sophisticated clocking and timing options, and two front panel QSFP cages, each supporting up to 100 Gbps (4×25). The A10PL4 also incorporates a Board Management Controller (BMC) for advanced system monitoring, which greatly simplifies platform management. Additional I/O interfaces include USB 2.0 and SATA.

S5PH-Q PCIe Board

BittWare’s S5PH-Q is a Gen3, x8 half-size PCIe card based on the high-bandwidth, power-efficient Altera Stratix V FPGA. The S5PH-Q is a versatile and efficient solution for high-performance network processing, signal processing, and data acquisition, with up to 16 GBytes of on-board DDR3 SDRAM and optional QDRII/II+ up to 72 MB (@ 550 MHz). I/O interfaces include two front-panel QSFP+ cages for serial I/O, two SATA connectors, and timestamping support, as well as RS-232, JTAG, and USB for debug.

Tools & Support

BittWorks II Toolkit-Lite

For system development tools, BittWare offers the BittWorks II Toolkit-Lite, which is a collection of utilities for BittWare’s Arria 10 and Stratix V boards. It provides utilities for board health and power monitoring as well as burning FPGA images to Flash. The Developer’s Bundle also includes a board support package for the A10PL4 or S5PH-Q

Altera® SDK for OpenCL

The Altera® SDK for OpenCL provides a design environment enabling users to easily implement OpenCL applications on Altera’s FPGAs.

Altera Quartus II

The OpenCL Developer’s Bundle includes the Altera Quartus II software, the complete software development package for the Altera Arria 10 and Stratix V FPGAs.

BittWare is a preferred board supplier for Altera OpenCL, and Altera has certified the S5PH-Q to support the OpenCL SDK.

What Is OpenCL

What is OpenCL?

The OpenCL (Open Computing Language) standard is the first royalty-free, open standard framework that enables users to write programs that execute across heterogeneous systems including CPUs (Central Processing Units), GPUs (Graphics Processing Units), DSPs (Digital Signal Processors), and FPGAs. It allows the use of a C-based language for developing code across these different platforms.

Developed by the Khronos Group, OpenCL greatly improves speed and responsiveness for many applications, including those in defense/aerospace, communications, high end instrumentation, life sciences, and financial.

OpenCL Benefits

What Are the Benefits of OpenCL for FPGAs?

  • Faster time-to-market using the OpenCL C-based parallel programming language as opposed to low-level hardware description language (HDL)
  • Quick design exploration by working at a higher level of design abstraction
  • Easy design re-use by re-targeting existing OpenCL C code to current and future FPGAs
  • Faster design completion by generating an FPGA implementation of OpenCL C code in a single step, bypassing the manual timing closure efforts and implementation of communication interfaces between the FPGA, host, and external memories.
  • Increased performance by offloading performance-intensive functions from the host processor to the FPGA
  • Significantly lower power by using the Altera SDK for OpenCL which generates only the logic needed to deliver

PCIe Financial Acceleration Platform (PRDP-FN)

    • Up to 16 BittWare PCIe boards
      • Up to 16 Arria 10, Arria V, or Stratix V FPGAs
      • Up to 32x 100GigE, 32x 40GigE or 128x 10GigE interfaces
    • 2U, 4U, or 5U rackmount PCIe system (server or expansion)
      • Up to two 8-core Intel® Xeon® processors
      • Up to 8 x16 PCIe slots
      • Up to 768 GB of memory
    • BittWorks II Development Tools

Overview

BittWare’s PCIe Financial Acceleration Platform is an application-ready server platform specifically designed for Financial Acceleration and High Frequency Trading (HFT) applications. This platform includes a PCIe 3.0 server or expansion system and arrives tested and configured, enabling designers to quickly deploy their financial applications. To further speed development, the system also supports a variety of financial application IP options.

2U, 4U, or 5U Rackmount PCIe System

The Financial Acceleration Platform is available with a variety of PCIe rackmount chassis options. Options include a 2U server system, a 4U server system, or a 5U expansion system.

Several 2U rackmount server system options are available from IBM/Lenovo, HP, or Dell. The 2U rackmount system supports up to two 12-core Intel Xeon processors and up to 768GB of memory (UDIMM/RDIMM/LRDIMM/HyperCloud DIMM). PCIe 3.0 x16 expansion slots accommodate BittWare’s full- and half-size PCIe boards.

The 4U server system supports a dual Intel Xeon (Ivy Bridge) processor with up to 12 cores, up to 768 GB of system memory, and can accommodate up to 8 double-wide x16 Gen3 PCIe boards. The 5U expansion system option features a PCIe Gen2 expansion system with eight double-width x16 slots and 80 Gbit/sec host bus-to-expansion system bandwidth.

BittWare Arria 10, Arria V, or Stratix V FPGA Boards

The Financial Acceleration Platform is available with up to eight BittWare FPGA PCIe boards based on the high-bandwidth, power-efficient Altera Arria 10, Arria V, or Stratix V FPGA. BittWare’s PCIe cards offer the industry’s highest performance FPGAs for network and algorithm acceleration, providing low latency with high-performance FPGA transceivers (no external PHY). Available memory types include DDR4 and DDR3 SDRAM, RLDRAM3, QDR-IV, and QDRII/II+. Front panel QSFP/SFP interfaces offer low-latency serial I/O.

BittWare’s FPGA DevKit provides a solid base for financial applications, including the following:

Financial Application IP Options

In addition to the firmware provided with BittWare’s FPGA DevKit, the Financial Acceleration Platform can also support a variety of third party IP for financial applications. IP supported includes Ultra low latency TOE, UOE, and MAC; low latency PCIe; high-bandwidth PCIe; book building and order management IP; and Market Data Feed Handler.

Software Support

BittWare offers complete software support for its PCIe boards with its BittWorks II software tools. The BittWorks II Toolkit is a collection of libraries and applications for BittWare’s Arria 10, Arria V, and Stratix V FPGA-based boards. Designed to make developing and debugging the applications for BittWare’s boards easy and efficient, the Toolkit provides the glue between the host application and the hardware. The Toolkit supports 32-bit, and 64-bit Windows and Linux platforms.

Specs

System Options

2U Server System

  • 2U rackmount (IBM/Lenovo, Dell, or HP)
  • Supports up to 6 Gen3 boards (2 x16, 4 x8)
  • Up to 2 Intel® Xeon® E5-2600 series processors, up to 12 cores
  • Up to sixteen 2.5” or six 3.5” HDDs or thirty two 1.8” SSDs
  • Up to 26 DIMM slots
  • Up to 768 GBytes system memory

4U Server System

  • 4U 17” rackmount chassis
  • 2+1 redundant power supply
  • Supports up to 8 double-wide Gen3 x16 (or 16 single-wide) boards
  • Dual Intel Xeon (Ivy Bridge) processor CPU with up to 12 cores each
  • Up to 768 GBytes system memory

5U PCIe Expansion System

  • PCIe Gen2 expansion system
  • 5U 19” rackmount chassis
  • N+1 redundant power supply
  • Supports up to 8 double-wide Gen2 x16 (or 16 single-wide) boards
  • 80 Gb/s host bus-to-expansion systems bandwidth
  • One or three meter expansion cable

Development Tools

  • BittWorks II Toolkit – host, command, and debug tools for BittWare hardware
  • FPGA Development Kit – FPGA board support IP and integration
  • OpenCL Developer’s Bundle – BittWorks II Toolkit, Altera SDK for OpenCL, Altera Quartus II
  • Altera Quartus II – tools for Arria 10, Arria V, and Stratix V FPGAs

PCIe Board Options

Board FPGA Form Factor Memory I/O
A10PL4 Arria 10 GX Low-profile PCIe x8 DDR4 SDRAM 2 QSFP+, Timestamp
A10P3S Arria 10 GX/SX 3/4-length PCIe x8 DDR4 SDRAM, QDR-IV 4 QSFP+, 2 SATA Express, Timestamp
A5PL Arria V GZ Low-profile PCIe x8 DDR3 SDRAM, QDRII+, RLDRAM3 2 QSFP+, Timestamp
S5PE-DS Stratix V GX/GS Full-length PCIe x16 DDR3 SDRAM, QDRII+, RLDRAM3 4 QSFP+, 8 SATA, Timestamp
S5PE-F Stratix V GX/GS Full-length PCIe x8 DDR3 SDRAMQDRII+RLDRAM3 VITA-57 siteExpansion site4 SATATimestamp
S5PH-Q Stratix V GX/GS Full-length PCIe x8 DDR3 SDRAMQDRII+ 2 QSFP+2 SATATimestamp

Ordering

Contact BittWare

ACC-S56X-BORT

  • 16 SerDes lanes to 4 QSFP connectors from expansion plane (P1)
  • 16 SerDes lanes to 4 QSFP connectors from data plane (P0)
  • Up to 2 SFP connectors for 1000Base-T
  • 2 RJ-45 connectors for 1000Base-T
  • Altera JTAG header
  • PCIe x1 standard external cabling connector
  • SATA connector
  • Headers for LVDS/single-ended on P3 and P4

Overview

BittWare’s ACC-S56X-BORT is a rear-transition breakout module for the S5-6U-VPX (S56X) board. It provides a convenient way to access the rear panel I/O signals on the S56X and provides support for using additional peripherals with the board. A variety of I/O connections are available to support the S56X board, including QSFP, Ethernet, PCIe, SATA, LVDS, and JTAG.

Thirty-two SerDes lanes are brought to eight* QSFP connectors, providing support for nearly any serial communication protocol, including 40GigE, 10GigE, Infiniband, or Fibre Channel. The SerDes lanes are also factory-configurable to provide loopback without using the external QSFP modules. Two* SFP connectors provide control plane access via GigE ultra thin pipe ports from P4. As an alternate option for control plane access, two RJ-45 connectors are available. I2C access is available to the QSFP and SFP modules from both the VPX backplane and headers.

A PCIe x1 port is routed to a standard external cabling connector for access to system control on the S56X. A host-side SATA connector connects external storage devices with the ARM Cortex A8 processor on the S56X. Eight headers provide access to the user-defined differential signals that come from the VPX connectors so that they can be sent off-board or looped back for testing. A JTAG header configured in the standard Altera pinout is available for debug access.

* The dataplane QSFP connectors and 1 SFP are on the back side of the board, requiring the use of the previous slot space.

Ordering

ACC-S56X-BORT-RW-AB-CDE-F
RW Ruggedization
2C = Conduction-Cooled Conformal Coating (-40C to 75C)*
A Expansion Plane Loopback
0 = Not Installed
1 = Installed
B Slot Count
1 = 1 slot (4 QSFPs, data plane loopback, 1 SFP)
2 = 2 slot (8 QSFPs, 2 SFPs) †
C VPX Key Position 1
1 = 0 Degrees
2 = 45 Degrees
3 = 90 Degrees
7 = 270 Degrees
8 = 315 Degrees*
9 = Unkeyed
D VPX Key Position 2
1 = 0 Degrees
2 = 45 Degrees
3 = 90 Degrees
7 = 270 Degrees
8 = 315 Degrees
9 = Unkeyed*
E VPX Key Position 3
1 = 0 Degrees
2 = 45 Degrees
3 = 90 Degrees
7 = 270 Degrees
8 = 315 Degrees
9 = Unkeyed*
F Envelope Assembly
6 = RoHS 6/6
P = SnPb assembly*

* Default
† Data plane QSFPs and second SFP are on the back side of the board, violating the previous slot space.

BWBO

  • Altera JTAG program header
  • DB-9 Serial Port
  • 10-pin header for a second serial port
  • 10/100-BaseT RJ45 jack (VPX only)
  • Micro-USB Connector
  • Fits into PCI slot (no connection to slot)
  • Attaches to host boards either through flat ribbon cable or pass-through header

Overview

The ACC-BWBO (BittWare BreakOut) board is used in development to gain access to several debug ports on BittWare’s S5 family boards. Due to space constraints, the actual S5 production boards cannot fit the standard connectors used for these debug ports, so the ACC-BWBO connects to the S5 board using a single high density connector (via included cable) and breaks these out into the industry standard connectors.

I/O Connectors

The connections provided for the S5 family of boards include Altera JTAG, RS-232, RJ-45, and USB. Support of these connectors depends on the S5 board the BWBO is used with. There is one RS-232 on the BWBO face plate, and another is available with a second cable breakout (provided). The RS-232s typically connect to the microcontroller used for monitoring power and temperature; the second RS-232 can be used with a UART instantiated in the Stratix V for user purposes.

An RJ-45 connector (used only for VPX boards) provides 10/100-BaseT, and a USB connector provides a host port for connecting slave devices such as Flash drives or keyboards to the host board.

Form Factor and Power

The ACC-BWBO is designed as a small PCI style board. It is powered by the host board and therefore takes no power from the slot; however, it has a small tab to allow it to be put in a PCI or PCIe slot as well as a standard faceplate.

Included Cables

All necessary cables are shipped with the ACC-BWBO. These include the following:

  • Flex cable for connecting the ACC-BWBO to the host board (supports full connection to host board)
  • Ribbon cable for alternate connection to host board (no support for USB)
  • IDC-to-DB9 cable for use with the 10-pin RS-232 connector

BWBO_cables

Block Diagram

BWBO-Block-Diagram

Ordering

ACC-BWBO-RW-AB-C
RW Ruggedization
0U = Commercial (0C to 50C)*
A Configuration Mode
2 = Altera JTAG USB Feed Through Mode*
B Mount Style
1 = PCI Faceplate*
C Envelope Assembly
6 = RoHS 6/6*

* Default

PCIe Industrial Platform (PRDP-IN)

    • Up to 16 BittWare PCIe boards
      • Up to 16 Arria 10, Arria V, or Stratix V FPGAs
      • VITA-57 FMC options: ADC, DAC, and transceiver cards
    • 4U or 5U rackmount PCIe system (server, industrial, or expansion)
      • 16-slot backplane support
      • Dual- or quad-core Intel® Xeon® processor SBC
      • Multiple front-access and internal drive bays
    • BittWorks II Development Tools

Overview

BittWare’s PCIe Industrial Platform (PRDP-IN) is an application-ready server platform specifically designed for industrial applications. Providing the processing power of up to sixteen Altera Arria® 10, Arria V, or Stratix® V Family FPGAs in an integrated system solution, the development platform is a completely stand-alone setup for designing and testing PCIe systems. It offers up to eight x16 PCIe slots, opening up a wide array of system configurations. The system arrives tested and configured, enabling designers to speed up the development process. And with the addition of BittWare’s BittWorks II tools, this platform allows users to fully design and debug in a flexible environment.

4U or 5U Rackmount Chassis

The PRDP-IN supports several chassis options. Options include 4U server and industrial systems and 5U industrial and expansion systems.

The 4U server system supports a dual Intel Xeon (Ivy Bridge) processor with up to 12 cores, up to 768 GB of system memory, and can accommodate up to 8 double-wide x16 Gen3 PCIe boards. The 4U industrial system offers dual and quad core options of the Intel Xeon Processor along with up to 193 GB DDR3 via mini DIMMs. A 14-slot backplane provides four x16 PCIe 2.0 slots as well as six PCIe x4 slots.

The 5U industrial system includes a 3.4GHz Xeon processor and supports up to eight double-wide Gen2 x16 boards. The 5U expansion system option features a PCIe Gen2 expansion system with eight double-width x16 slots and 80 Gbit/sec host bus-to-expansion system bandwidth.

BittWare FPGA PCIe Boards

The development platform is available with up to 16 BittWare PCIe boards based on the Altera Arria 10, Arria V, and Stratix V FPGAs. BittWare offers a variety of PCIe boards to meet our customers’ specific requirements, including full-size, half-length, 3/4-length, and low-profile. The boards support several memory types, including DDR4, DDR3, RLDRAM3, and QDRII/II+. Additional board features include QSFP/SFP for high-speed serial I/O and FMC and expansion interfaces for I/O.

PCIe Board I/O Options

A variety of A/D, D/A, transceiver, and processor FMC I/O modules are available to expand the system’s I/O capabilities. All BittWare Stratix V-baed PCIe boards support a debug breakout board (BittWare BWBO) to provide front-panel access via USB, JTAG, RS-232, and Ethernet.

Software Support

BittWare offers complete software support for its PCIe boards with its BittWorks II software tools. The BittWorks II Toolkit is a collection of libraries and applications for BittWare’s Arria 10, Arria V, and Stratix V FPGA-based boards. Designed to make developing and debugging the applications for BittWare’s boards easy and efficient, the Toolkit provides the glue between the host application and the hardware. The Toolkit supports 32-bit, and 64-bit Windows and Linux platforms.

Specs

4U Industrial System

      • Compact 4U 19” rack mount (Trenton Systems TCS4501)
      • High-performance computing system power supply (single ATX/EPS P/S up to 1500 W)
      • Supports up to 4 double-wide Gen3 x16 boards
      • 14-slot backplane configuration
      • Intel® Xeon® dual- or quad-core processor

4U Server System

      • 4U 17” rackmount chassis
      • 2+1 redundant power supply
      • Supports up to 8 double-wide Gen3 x16 boards
      • Dual Intel Xeon (Ivy Bridge) processor CPU with up to 12 cores each
      • Up to 768 GBytes system memory

5U PCIe Expansion System

      • PCIe Gen2 expansion system
      • 5U 19” rackmount chassis
      • N+1 redundant power supply
      • Supports up to 8 double-wide (or 16 single-wide) Gen2 x16 boards
      • 80 Gb/s host bus-to-expansion systems bandwidth
      • One or three meter expansion cable

5U Industrial System

      • 5U 19” rackmount chassis
      • N+1 redundant power supply
      • Supports up to 8 double-wide (or 16 single-wide) Gen2 x16 boards (Gen3 x16 available soon)
      • 3.4GHz Xeon processor SBC (other SBC options available)
      • Front access hard disk drive carriers and DVD media bay
      • High CFM fan with controller

VITA 57 FMC Options (for S5PE-F only)

      • 3F104: 4 channels 14-bit, 250 MSPS ADC
      • 3F107: 8 channels 12-bit, 65 MSPS ADC
      • 3F125: 1 to 4 channels 8-bit, up to 5 GSPS ADC
      • 3F126: 1 to 4 channels 10-bit, up to 5 GSPS ADC
      • 3F204: 1 or 2 channels 16-bit, up to 1 GSPS DAC
      • 3F230: 2 channels 14-bit, 5.6 GSPS DAC
      • 3F150: 2 channels 14-bit, 250 MSPS ADC and 2 channels 16-bit, 250 MSPS DAC
      • BittWorks II Toolkit – host, command, and debug tools for BittWare hardware
      • FPGA DevKit – FPGA board support IP and integration
      • Altera Quartus II – tools for Arria 10, Arria V, and Stratix V FPGAs

PCIe Board Options

Board FPGA Form Factor Memory I/O
A10PL3 Arria 10 GT/GX Low-profile PCIe x8 DDR3 SDRAM Timestamp
A10P3S Arria 10 GT/GX/SX 3/4-length PCIe x8 DDR4 SDRAM
QDR-IV
4 QSFP+
2 SATA Express
Timestamp
A10PHQ Arria 10 GT/GX/SX Half-length PCIe x8 DDR4 SDRAM
QDR-IV
2 QSFP+
2 SATA
Timestamp
A5PL Arria V GZ Low-profile PCIe x8 DDR3 SDRAM
QDRII+
RLDRAM3
2 QSFP+
Timestamp
S5PE-DS Stratix V GX/GS Full-length PCIe x16 DDR3 SDRAM
QDRII+
RLDRAM3
4 QSFP+
8 SATA
Timestamp
S5PE-F Stratix V GX/GS Full-length PCIe x8 DDR3 SDRAM
QDRII+
RLDRAM3
VITA-57 site
Expansion site
4 SATA
Timestamp
S5PH-Q Stratix V GX/GS Full-length PCIe x8 DDR3 SDRAM
QDRII+
2 QSFP+
2 SATA
Timestamp

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