BittWare Partner IP MACsec IP Core IEEE 802.1AE IP Core The Xiphera MACsec family provides high-speed IP cores implementing the MACsec (Media Access Control security) protocol as standardized in IEEE Std 802.1AE-2018. The MACsec protocol defines a security infrastrucure for Layer 2 (as per the OSI model) traffic by assuring
Category: IP Core
BittWare Partner IP Core RDMA Low-Latency RoCE v2 at 100Gbps The GROVF RDMA IP core and host drivers provide RDMA over Converged Ethernet (RoCE v2) system implementation and integration with standard Verbs API. The RDMA IP is delivered with a reference design that includes the IP subsystem itself, the 100G
BittWare Partner IP Query Processing Unit (QPU) Build FPGA-powered accelerators to query, analyze or reformat stored or streaming data at PCIe Gen4 speeds! Eideticom’s Query Processing Unit (QPU) targets database users or anyone streaming data (such as network packets) who need query, analytics or format conversion done in hardware with
BittWare Partner IP Core UDP Offload Engine IP Core UOE IP Core for 10/25/50/100GbE Atomic Rules UDP Offload Engine (UOE) is a UDP FPGA IP Core that allows for immediate operation at 10, 25, 40, 50, or 100GbE. The UOE IP core implements the UDP standard RFC 768, including checksum,
BittWare Partner IP TimeServo IP Core High Performance System Timer IP The TimeServo IP core by Atomic Rules is an RTL IP core that serves the function of an FPGA’s system timer or clock. Although specifically designed to support the needs of line-rate independent packet timestamping, TimeServo may find use
PCIe Gen4 data mover IP from Atomic Rules. Achieve up to 220 Gb/s using BittWare’s PCIe Gen4 cards, saving your development team when you need more performance than standard DMA. Features: DPDK and AXI standards, work with packets or any other data format, operate at any line rate up to 400 GbE.