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XUSPL4

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Xilinx UltraScale Low-Profile PCIe Board with Dual QSFP and DDR4
    Application
  • NPP Network Packet Processing
  • HPC High Performance Computing
  • SP Signal Processing
  • NPP HPC SP
    Market
  • C&D Compute & Data Center
  • GOV Government
  • I&T Instrumentation & Test
  • FIN Financial Services
  • B&V Broadcast & Video
  • C&D GOV I&T FIN B&V
Features
  • Xilinx Virtex UltraScale 65/95 or Kintex UltraScale 95
  • Up to two PCIe x8 interfaces supporting Gen1, Gen2, or Gen3
  • Two QSFP28 cages for 2x 100GbE, 2x 40GbE, 8x 25GbE, or 8x 10GbE
  • Memory: up to 32 GBytes of DDR4 SDRAM with ECC (x72)
  • Board Management Controller for Intelligent Platform Management
  • Precision timestamping support
  • Utility I/O: USB 2.0
Overview

BittWare’s XUSPL4 is a low-profile PCIe x8 card based on the Xilinx Virtex or Kintex UltraScale FPGA. The high-performance UltraScale devices provide increased system integration, reduced latency, and high bandwidth for systems demanding massive data flow and packet processing. The board offers up to 32 GBytes of memory, sophisticated clocking and timing options, and two front panel QSFP cages, each supporting up to 100 Gbps (4×25) – including 100GbE. The XUSPL4 also incorporates a Board Management Controller (BMC) for advanced system monitoring, which greatly simplifies platform integration and management. All of these features combine to make the XUSPL4 ideal for a wide range of data center applications, including network processing and security, acceleration, storage, broadcast, and SigInt.

Xilinx Virtex or Kintex UltraScale FPGA

The Xilinx UltraScale FPGAs are built on 20 nm process technology and provide ASIC-like clocking for scalability, performance, and lower dynamic power. UltraScale devices are available in two variants: Virtex and Kintex; the XUSPL4 board supports both. The FPGAs feature two types of multi-gigabit transceivers: Virtex devices support up to 30 Gbps, enabling 100 GbE and 25 GbE, while Kintex devices support up to 16 Gbps, enabling 40 GbE and 10GbE. The GTY transceivers enable 100GbE and 25GbE. The FPGAs support 768 DSP slices. The UltraScale FPGAs provide four integrated blocks for PCI Express, supporting x8 Gen3 Endpoint and Root Port designs. Integrated blocks for 100 Gb/s Ethernet (100G MAC/PCS) enable simple, reliable support for Nx100G switch and bridge applications.

I/O Interfaces

The XUSPL4 provides a variety of interfaces for high-speed serial I/O as well as debug support. Two QSFP28 cages are available on the front panel, each supporting 100GbE, 40GbE, four 25GbE, or four 10GbE channels, for a total of up to 200 Gbps of bandwidth. The QSFP channels are connected directly to the UltraScale FPGA via 32 Gb/s transceivers (or 16 Gb/s for Kintex devices). The QSFP cages can optionally be adapted for SFP+.

Two Gen3 x8 PCIe interfaces connect to the FPGA via 16 transceivers, allowing for a x8 PCIe connection in a standard slot or two x8 interfaces in a bifurcated slot. A USB 2.0 interface provides BMC access. The board also supports precision timestamping with provision for a 1 PPS and reference clock input and output.

Memory

The XUSPL4 features up to 32 GBytes DDR4 on-board. Additional on-board memory includes Flash with factory default and support for multiple FPGA images.

Board Management Controller

The XUSPL4 features an advanced system monitoring subsystem, similar to those typically found on today’s server platforms. At the heart of the board’s monitoring system lies a Board Management Controller (BMC), which accepts Intelligent Platform Management Interface (IPMI) messaging protocol commands. The BMC provides a wealth of features, including control of power and resets, monitoring of board sensors, FPGA boot loader, voltage overrides, configuration of programmable clocks, access to I2C bus components, field upgrades, and IPMI messaging. Access to the BMC is via PCIe or USB. BittWare’s BittWorks II Toolkit also provides utilities and libraries for communicating with the BMC components at a higher, more abstract level, allowing developers to remotely monitor the health of the board.

BwMonitor in the BittWorks II Toolkit provides a view into the board management capabilities of your BittWare hardware.

Development Tools

BittWorks II Toolkit

BittWare offers complete software support for the XUSPL4 with its BittWorks II software tools. Designed to make developing and debugging applications for BittWare’s boards easy and efficient, the Toolkit is a collection of libraries and applications that provides the glue between the host application and the hardware. A variety of features allow developers to take full advantage of the Xilinx UltraScale FPGA capabilities on the BittWare board, including FPGA control via PCIe, Flash programming, custom ISR scripts, and convenient control of FPGA loads. The Toolkit supports 32-bit, and 64-bit Windows and Linux platforms and can connect to the board via PCIe or USB, providing a common API no matter the connection method.

FPGA Development Kit

BittWare’s FPGA Development Kit (FDK) provides FPGA board support IP and integration for BittWare’s FPGA-based boards. The FDK includes FPGA components that provide preconfigured physical interfaces, infrastructure, and examples, drastically cutting development time and easily integrating into existing FPGA development environments.

Working example projects are available for each board which illustrate how to move data between the board’s different interfaces. Supported interfaces include DDR4, QDR-IV, QDR-II+, PCIe, 10GbE, LVDS, SerDes, and Double Data Rate I/O.

Specifications

Specifications

Board Specifications

FPGA

  • Up to 940K logic elements
  • Up to 60 Mb of embedded memory
  • Up to 4 integrated PCIe cores
  • Up to 768 DSP slices with 27×18 multipliers
  • Xilinx UltraScale FPGA
    • Virtex UltraScale 65/95
    • Kintex UltraScale 95
  • Multi-gigabit transceivers
    • Virtex: 8 GTY at 30.5 Gbps and 17 GTH at 16 Gbps
    • Kintex: 25 GTH at 16 Gbps

On-Board Memory

  • Two banks of up to 16 GB DDR4 (x72)
  • Flash memory for booting FPGA

PCIe Interface

  • Two x8 Gen1, Gen2, Gen3 interfaces direct to FPGA (One x8 interface in a standard slot; two x8 interfaces requires bifurcated slot)

USB Header

  • Micro USB port (USB 2.0) for BMC access and programming Flash

QSFP Cages

  • 2 QSFP28 (zQSFP) cages on front panel connected directly to FPGA via 16 GTY transceivers (GTH for Kintex)
  • Each supports 100GbE, 40GbE, 4x 25GbE, or 4x 10GbE (100GbE, 25 GbE Virtex only)
  • Backward compatible with QSFP and can be optionally adapted for use as SFP+

Timestamping

  • 1 PPS input/output
  • Reference clock input/output

Board Management Controller

  • Voltage, current, temperature monitoring
  • Power sequencing and reset
  • Field upgrades
  • FPGA configuration and control
  • Clock configuration
  • I2C bus access
  • USB 2.0
  • Voltage overrides

Size

  • Low profile (Half-height, half-length) PCIe slot card; x16 mechanical

Development Tools

System Development

  • BittWorks II Toolkit – host, command, and debug tools for BittWare hardware; Matlab API; source code porting kit also available

FPGA Development

  • FPGA Development Kit
    • Physical interface components
    • Board, I/O, and timing constraints
    • Example projects
    • Software components and drivers
  • Xilinx Tools
    • Vivado® Design Suite
    • USB to JTAG converter
Block Diagram

Ordering Options

XUSPL4 Ordering Options

XUSPL4-RW-ABBBBCD-EF-GIJKL-MO
RW Ruggedization

0U = Commercial (0°C to 50°C)*

A UltraScale Printed Wiring Board

  • A = Optimized for 95 FPGA
  • C = Optimized for 65 FPGA*
BBBB FPGA Type and Size

  • 065V = Virtex VU065*
  • 095K = Kintex KU095
  • 095V = Virtex VU095
C FPGA Core Speed Grade

  • 1 = Slower
  • 2 = Nominal
  • 3 = Faster
  • H = Nominal (-1HV) *‡
D FPGA Temperature Range

E = Extended (Tj = 0 to +100C)*

E DDR4 Bank A

  • 0 = None
  • 2 = 4GB*
  • 3 = 8GB
  • 4 = 16GB†
F DDR4 Bank B

  • 0 = None
  • 2 = 4GB*
  • 3 = 8GB
  • 4 = 16GB†
G Oscillator

S = Standard*

I QSFP Configuration

2 = 2 QSFP cages

J JTAG

1 = Installed*

K Front Panel Configuration

  • F = Full-height
  • H = Half-height*
  • T = Full-height with Precision Timing Module
P Heatsink

A = Active

Q Misc. Configuration

0 = Default

R Assembly

6 = RoHS 6/6

* Default.

† Contact BittWare.

‡ For Virtex VU065 FPGA only.

Software Support
BittWare UltraScale Board Software Support
BittWare Feature UltraScale Family
Program Flash
via PCIe
via USB


Configure FPGA From Flash
via PCIe
via USB

Configure FPGA Directly via USB
Reset FPGA
via PCIe
via USB


Access FPGA Registers, Memory Spaces From User Applications
via PCIe
via USB


Virtual PCIe Hot-Swap
On-board JTAG Pod
Factory Backup Image with PCIe
Multiple User Images in Flash
Serial Number
via PCIe
via USB


MAC Addresses For Each Network Interface
via PCIe
via USB


BMC Voltage, Current, Temperature Sensors
via PCIe
via USB


BMC Clock Re-programming
via PCIe
via USB


BMC FPGA Core Voltage Override
via PCIe
via USB


Upgrade BMC Firmware
via PCIe
via USB


Documentation
Quick-start Guide
User’s Manual
How-to Index
BMC User’s Guide



Examples
PCIe DMA
10G Ethernet
DDR4 Memory
BMC Host (without using BittWare drivers)




Why BittWare?

Quality & Life Cycle Management

Technology refresh capability with 10+ year supply, quality and timely manufacturing and a trustworthy supply chain. ISO 9000 certified FPGA platform vendor with a history of proven, successful, on-time supply.  Learn more.

FPGA Board Platforms

BittWare's Virtex and Kintex UltraScale low-profile and 3/4-length PCIe board platforms support dual & quad QSFP, DDR4, configurable hardware options, data conversion I/O options, and air-cooled operation.  Learn more.

FPGA Development Tools

Designed to make developing and debugging the applications for BittWare’s boards easy and efficient, the Toolkit provides the glue between the host application and the hardware.  Learn more.

System Development & Integration

Host development tools, Board Support Packages, Baseboard Management Controller and integrated platforms including chassis, backplanes for a full solution. Learn more.

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