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10/25/40/100G Ethernet Filter IP Core for FPGA

Preliminary
Advanced Network Filtering IP Core
    Application
  • NPP Network Packet Processing
  • HPC High Performance Computing
  • SP Signal Processing
  • NPP    
    Market
  • C&D Compute & Data Center
  • GOV Government
  • I&T Instrumentation & Test
  • FIN Financial Services
  • B&V Broadcast & Video
  • C&D GOV      
Features
  • Industry standard IEEE 802.3 interface
  • 10/25/40/100G line rates
  • Deep packet inspection of all layers of the OSI model
  • Modular scalable design adjusts to fit any size application
  • Transparent processing without modifying packet data
  • PCAP syntax expression synthesizer
  • Minimum term computation algorithm for maximum resource efficiency
  • Generic VHDL code can easily be implemented in any technology
  • Packet sizes up to 16Kbytes
  • Can be adapted to filter any packetized protocol, not limited to Ethernet
Overview

The IEEE 802.3 10G/25G/40G and 100G Ethernet Filter IP Core from BittWare provides a hardware-scalable solution that is capable of identifying characteristics of Ethernet frames on all seven layers of the OSI model at line rate. The user enters search terms via a configurable PCAP syntax expression parser and rule synthesizer. The core can be scaled from one filter rule to thousands of rules limited only by hardware resources available. No IP or MAC address is required for operation, allowing for transparent insertion into the network being monitored.

Product Description

The Ethernet Filter core provides a single line-rate receive/transmit data path that is compliant with any IEEE 802.3 PHY-to-MAC interface:

Each frame presented to the core is analyzed by filter-logic that determines if the frame’s data contents match a set of industry-standard PCAP ASCII expressions. The logic and PCAP ASCII expressions are not limited to the top-layers of the frame. The entire frame’s data contents are accessible including the Preamble, Start-of-Frame Delimiter, and CRC; this allows for deep packet inspection of all OSI Layers (1 through 7) at line rate. The latency of each frame is static and is proportional to the resources allocated. Frames matching the user-configured set of expressions are identified by a packet-match logical output driven synchronously with the frame on the transmit Interface.

Ethernet data frames presented on the speed selectable PHY-to-MAC input interface are passed through the filter unmodified regardless of the frame’s data contents. This includes the preamble and CRC. Frame sizes up to 16Kbytes are supported.

Custom embeddable software interprets the user input PCAP ASCII expressions and synthesizes them into a hardware configuration HEX file that can be directly loaded into filter resources through the management interface. 8-bit parallel and serial interfaces are available for expression loading. Along with the synthesized HEX file, the software synthesizer provides top-level instantiation information which provides the minimum set of resources that are required for the IP to filter against the user-developed PCAP ASCII expressions. The expression synthesizer features a minimum term computation algorithm to ensure the most efficient possible use of resources. This software is not platform specific and can be run on Windows, Linux, and any embedded microprocessors.

The fully-scalable modular design allows a user to size the filter resources as required by the application. The IP can be instantiated with a minimum number of resources to support as little as a single PCAP ASCII expression. Conversely, the IP can be expanded to support any number of resource blocks to cover the PCAP ASCII expressions required by the application. The number of resource blocks that can be instantiated is only limited by the number of resources available on the target device/architecture. This flexible nature of the design allows for massively serial and/or parallel architecture implementation in any duplex configuration.

Custom software drivers interpret the user input PCAP ASCII expressions and synthesize them into minimum terms for the most efficient use of hardware filtering resources. Resources are then divided and placed in different locations within the processing fabric to ensure optimum traffic flow and analysis. Many packet broker systems use PCAP processing expressions, but BittWare’s point-to-point fabric is the first in the industry to optimize user inputs before loading resource settings. This allows more rules to be packed into a smaller space and increases packet processing efficiency. RMON statistics counters and fabric settings are available via driver API calls.

Deliverables

Block Diagram

Ordering Options

Ordering Information

Contact BittWare for details.


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