Knowledge Database

DSP Boards

The following is a list of topics relating to BittWare's DSP boards.

General

• What are the speeds of the Cluster bus on your boards?
• Is it possible to connect to and debug a Flash loaded DSP in standalone mode?
• Where do I find processor manuals and VDSP manuals?
• Is BittWare still offering it's Audio-PMC+ board to new customers?
• What are the part numbers for the Rocket I/O (J1, J2) and the DIO breakout connectors (J6A, J7A) on the T2-PCI (T2PC) board?
• What is the availability of the User Constraints File (UCF) required on BittWare boards utilizing FPGAs?
• What are the environmental specifications of your boards?
• Does BittWare still provide support for the EZ-KIT Lite Evaluation systems?
• Which jumpers does BittWare use on their boards?
• When there are multiple DSP's writing to the same region of SDRAM, what is the best method to implement a "lockout" feature, allowing the current DSP to complete its data cycle before any other DSPs are allowed access to the same SDRAM area?
• Are there any examples for your boards?

Danube-6Pac-PCI

• What are the DMAR mappings on a Danube 6-PaC PCI (D6PC) board?
• What is the mating connector to the Danube 6-PaC PCI (D6PC) link port connectors.
• Why is DspTest failing the SDRAM on my Danube 6-PaC PCI (D6PC) board?
• What connector is used on board for the Danube 6-PaC PCI (D6PC) link port?

Tiger (TS101)

• What is the information that is passed back from the board when using the dsp21k_int functions?
• What is the expected power consumption for the Tiger-PCI (TSPC)?
• Is the Tiger-6U-cPCI (TS6U) compatible with the PXI standard?
• Can BittWare recommend right-angle mounted Link Port Cables for the Tiger-PCI (TSPC)?
• Why can't I get 512 MByte SDRAM on my Tiger board?
• What is the transfer rate from the DSP to the SDRAM on a Tiger-PCI (TSPC) board?

T2 (TS201)

• How do I control and change the SYSCON & SDRCON settings on my TS201-based board?
• What are the different ways to transfer data between two T2-PCI (T2PC) boards?
• What is the recommended manufacturer and part number for the T2-PCI DIO cable assemblies?
• If I would like to implement the ATLANTiS SERDES Block within a non-ATLANTiS FPGA, how do I obtain the wrapper and supporting material to compile my FPGA?
• Regarding the Atlantis Architecture, there are 2 Muxes available in the FPGA to connect various peripherals together. Does this meant that it you can only have two simultaneous data flows in the FPGA, i.e., one link port sending information to one Rocket I/O on one Mux and another link port sending information to another port?
• What are the characteristics of the AURORA protocol implemented on the Atlantis FPGAs and available on the Rocket I/O links?
• Why isn't the serial loopback on my RocketIOs working properly?
• When using ATLANTiS to switch Link Ports or RocketIO ports, why do I sometimes get duplicating data at the receiver?

Hammerhead

• What are the Hammerhead-6U-cPCI (HH6U) power requirements?
• What is the SDRAM Window on a Hammerhead board used for?
• What are the SDRAM speed requirements for BittWare's Hammerhead 21160 DSP boards?
• Is the Hammerhead-3U-cPCI (HH3U) PXI compliant?
• What are the power requirements for the Hammerhead-PCI (HHPC)?

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