ATLANTiS FrameWork (AFW)

AFW provides the quickest path to deployment through proper validation by supporting software simulations and providing hooks for improved on-board testing.

• Scripted simulation control
• Standard data generators such as random, sine, cosine, sequence, pattern, file
• Verification and diagnostic components such as comparison, capture, threshold, BER, file
• Bus Functional Models (BFM) for each physical interface, including memory models

AFW resources allow users to simulate the whole FPGA project, saving them the time and cost of developing these resources themselves.

AvalonSTFileReader
Used to read a data input file during simulation and create Avalon-ST transactions that drive the component under test

AvalonSTFileWriter
Captures the results from the Avalon-ST interface of the component under test and writes the results to a file for validation and post processing

ClkGen
Used to create clocks for simulation at specified frequencies and phases

PatternGenerator
Creates all sorts of test patterns for simulation and board test

SequenceGenerator
Used to create different types of one- and two-dimensional sequences

SimulationController
Speeds up simulation efforts; reads a command file and translates it to an Avalon-MM master interface that is used to set up the component under test and other simulation components

SinkCompare
Used to compare Avalon-ST data interface component data with expected results

SinkComponent
Validates/tests Avalon-ST component interface outputs

SlaveComponent
Used to verify the operation of a component that uses the Avalon-MM slave interface

Timer
Allows the host to time operations to a fine resolution