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AFW provides all the other necessary pieces to quickly create and modify simulation and synthesis projects. Scripting of project creation, simuations, and synthesis simplifies each phase of development.
- Example and template projects leveraging validated physical interfaces can be used as a starting point
- Example processing components including test benches
- Standard components for clocking and resets
- Fully scripted timing constraints and I/O configurations
- Path to SOPC and VisualDSP Builder design flow
GT Links
Demonstrates the link ports on BittWare GT family products containing the Analog Devices DSPs
GT/GX DDR2
Demonstrates the DDR2 interfaces on each of the BittWare Stratix II GX boards
GT/GX/S4 SLite
Demonstrates the different SerDes lanes on each of BittWare's boards
GT/S4 DDIO
Demonstrates the DDIO interface on the GT and S4 families of boards
S4 DDR3
Demonstrates the performance of simultaneous memory access of the board's DDR3 banks
S4 FINe
Demonstrates host access on the S4 family boards
S4 MiscIO
Simple I/O demonstration on S4 family boards
S4 QDR2
Demonstrates the QDR2 memory component and allows access to QDR2/+ memory on S4 boards
ExampleComponent
Used as a reference for new developers to describe how to set up and configure a component
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