ATLANTiS FrameWork (AFW)

Not all Avalon Memory Mapped Interfaces are the same. Address and data widths, pipelined or not, byte enables, master or slave, bursting, read latency, and more can vary between components.

AFW provides:

• Memory mapped fabrics, including address decoding and arbitration
• Interrupt handlers
• Reset infrastructure
• Storage, such as dual port memory and register banks

Available Components:

AvalonMasterToSlave
Converts Avalon-MM master transactions into Avalon-MM slave transactions

Arbiter
Provides multiple access from a varied number of slaves to a single Avalon-MM interface

DMAController
Generates Avalon-MM DMAs by utilizing multiple DMAReader and/or DMAWriter engines

DMAReader
Performs DMA reads from an Avalon-MM slave and writes the response to an Avalon-ST source interface

DMAWriter
Performs DMA writes to an Avalon-MM slave interface sourced by an Avalon-ST interface

IRQDecoder
Decodes Avalon-IRQ sender interrupts

Memory
Provides a wrapper around the FPGA device specific RAM memory core

MasterDecoder
Decodes Avalon-MM master addresses to multiple Avalon-MM slaves

RegisterBank
Used to manage component control, configuration, and status

SlaveDecoder
Decodes Avalon-MM slave addresses to multiple Avalon-MM slaves

SlaveFIFO
A bidirectional Avalon-MM FIFO

SlaveWindow
Used to open up address space on an Avalon-MM bus