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Arbiter
Provides multiple access from a varied number of slaves to a single Avalon-MM interface
DMAController
Generates Avalon-MM DMAs by utilizing multiple DMAReader and/or DMAWriter engines
DMAReader
Performs DMA reads from an Avalon-MM slave and writes the response to an Avalon-ST source interface
DMAWriter
Performs DMA writes to an Avalon-MM slave interface sourced by an Avalon-ST interface
IRQDecoder
Decodes Avalon-IRQ sender interrupts
MasterDecoder
Decodes Avalon-MM master addresses to multiple Avalon-MM slaves
MasterToSlave
Converts Avalon-MM master transactions into Avalon-MM slave transactions
Memory
Provides a wrapper around the FPGA device specific RAM memory core
MemoryMappedTester
Automates the testing of an Avalon-MM slave interface
Nios
Wrapper around the Altera Nios processor allowing users to implement it without the use of SOPC Builder
PacketDMAController
Generates Avalon-ST DMAs by utilizing multiple PacketDMAReader and/or PacketDMAWriter engines
PacketDMAReader
Performs DMA reads from an Avalon-ST packet interface and writes the response to an Avalon-ST typical interface
PacketDMAWriter
Writes AFW write request packets to an Avalon-ST interface sourced by an Avalon-ST input interface
PacketGenerator
Test component that generates a stream of AFW Packets
PacketSwitch
Routes AFW Avalon-ST packets between different packet nodes within the FPGA
PacketTargetMaster
Accepts and converts AFW Avalon-ST packets to Avalon-MM transactions
RegisterBank
Used to manage component control, configuration, and status
RxLVDS
High speed LVDS receiver that supports chip to chip communication and ADC/DAC interfaces
SlaveDecoder
Decodes Avalon-MM slave addresses to multiple Avalon-MM slaves
SlaveFIFO
A bidirectional Avalon-MM FIFO
SlaveWindow
Used to open up address space on an Avalon-MM bus
StreamingTester
Automates the testing of a variable number of Avalon-ST input and output interfaces
TxLVDS
High speed LVDS transmitter that supports chip to chip communication and ADC/DAC interfaces
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