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ATLANTiS Component Library
An ATLANTiS FrameWork component is an FPGA element that offers a predefined service. It is able to communicate with other components through a well-defined interface and thus, when connected to other components, the services work together to build complete projects. The ATLANTiS FrameWork component library includes the following:
Physical Interfaces
- DDR3Memory: provides the DDR3 memory controller and physical interface to access external memory
- DDR2Memory: provides the DDR2 memory controller and physical interface to access external memory
- DDIOMaster: general purpose DDIO based interface for transferring memory mapped command and status board to board or device to device
- DDIOSlave: general purpose DDIO based interface for transferring Avalon-MM slave interface transactions board to board or chip to chip
- RxDDIO: uses Altera’s double data rate (DDR) I/O primitive for general purpose data transfer
- TxDDIO: uses Altera’s double data rate (DDR) I/O primitive for general purpose data transfer
- QDR2Memory: allows access to QDR2/QDR2+ memory on BittWare boards
- FINe : interfaces to the FINe on BittWare boards
- PLL: derives custom internal clocks from external clocks
- RxLinkPort: allows FPGA to receive data from a TigerSHARC link port
- TxLinkPort: sends data to a TigerSHARC link port
- ClusterBus: responsible for communication from Analog Devices’ TigerSHARC and/or FINe processors
Streaming Data Interconnect
- FIFO: can be configured to different bit widths and depths or to operate in multi-rate or single-rate mode
- Reshape: restructures streaming data to different bit widths and data rates
- SlaveToStreaming: converts an Avalon-MM slave interface to an Avalon-ST interface
- SlaveWriteToStreaming: converts Avalon-MM slave write transactions to Avalon-ST source transactions
- StreamingBuffer: allows streaming data input and output flexibility while reducing the amount of redundant code supporting each streaming component interface
- StreamingToMaster: converts Avalon streaming data transactions to Avalon-MM master read and write transactions
- StreamingToSlaveReadRsp: translates Avalon-ST input data to an Avalon-MM slave read response
- Switch: can connect any number of inputs to any number of outputs and can be configured to operate in multiple modes: static, priority, simple mux, bursting, etc.
Control and Memory Management
- Arbiter: provides multiple access from a varied number of slaves to a single Avalon-MM interface
- DMAController: Generates Avalon-MM DMAs by utilizing multiple DMAReader and/or DMAWriter engines
- DMAReader: performs DMA reads from an Avalon-MM slave and writes the response to an Avalon-ST source interface
- DMAWriter: performs DMA writes to an Avalon-MM slave interface sourced by an Avalon-ST interface
- IRQDecoder: decodes Avalon-IRQ sender interrupts
- Memory: provides a wrapper around the FPGA device specific RAM memory core
- MasterDecoder: decodes Avalon-MM master addresses to multiple Avalon-MM slaves
- MasterToSlave: converts Avalon-MM master transactions into Avalon-MM slave transactions
- MemoryMappedTester: automates the testing of an Avalon-MM slave interface
- Nios: wrapper around the Altera Nios processor allowing users to implement it without the use of SOPC Builder
- PacketDMAController: Generates Avalon-ST DMAs by utilizing multiple PacketDMAReader and/or PacketDMAWriter engines
- PacketDMAReader: performs DMA reads from an Avalon-ST packet interface and writes the response to an Avalon-ST typical interface
- PacketDMAWriter: writes AFW write request packets to an Avalon-ST interface sourced by an Avalon-ST input interface
- PacketGenerator: test component that generates a stream of AFW Packets
- PacketSwitch: routes AFW Avalon-ST packets between different packet nodes within the FPGA
- PacketTargetMaster: accepts and converts AFW Avalon-ST packets to Avalon-MM transactions
- RegisterBank: used to manage component control, configuration, and status
- RxLVDS: high speed LVDS receiver that supports chip to chip communication and ADC/DAC interfaces
- SlaveDecoder: decodes Avalon-MM slave addresses to multiple Avalon-MM slaves
- SlaveFIFO: a bidirectional Avalon-MM FIFO
- SlaveWindow: used to open up address space on an Avalon-MM bus
- StreamingTester: automates testing of a variable number of Avalon-ST input and output interfaces
- TxLVDS: high speed LVDS transmitter that supports chip to chip communication and ADC/DAC interfaces
SerDes Protocols
- 10 GigE*: uses 10 GigE interface standard for high-speed data transfer
- PCIe: uses the Altera PCIe Hard IP core to provide a PCIe end point solution
- SerialLite: uses the Altera SerialLite II solution for high-speed SerDes transfer
- SerialRapidIO*: uses the Serial RapidIO standard for high-speed SerDes transfer
Example Components
- ComponentTemplate: skeleton of a VHDL file that can be used as a starting point for new development
- ExampleComponent: used as a reference for new developers to describe how to set up and configure a component
- ExampleSubSystem: demonstrates how to tie together streaming data paths with memory mapped data paths
Utility Libraries and Resources
- AvalonPkg: defines all supported Avalon interface profiles
- BoardInfoPkg: contains all board and device specifications
- Counter: basic programmable counter that can be used as a subcomponent
- ComponentPkg: contains a constant component ID for each ATLANTiS FrameWork component
- ComponentTemplate: component wrapper template for use as a starting point for custom processing components
- SoftReset: used to generate a soft reset signal synchronized to the provided input clock
- SynchPulse: used to synchronize a pulse across two different clock domains
- SynchRegister: assists in crossing clock domains, typically in a control data path
- SynchReset: used to retime asynchronous resets to a given time domain
- UtilityPkg: contains functions, procedures, and constants to aid in development
Simulation and Test
- AvalonSTFileReader: used to read a data input file during simulation and create Avalon-ST transactions that drive the component under test
- AvalonSTFileWriter: captures the results from the Avalon-ST interface of the component under test and writes the results to a file for validation and post processing
- ClkGen: used to create clocks for simulation at specified frequencies and phases
- PatternGenerator: creates all sorts of test patterns for simulation and board test
- SequenceGenerator: used to create different types of one- and two-dimensional sequences
- SimulationController: speeds up simulation efforts; reads a command file and translates it to an Avalon-MM master interface that is used to set up the component under test and other simulation components
- SinkComponent: validates/tests Avalon-ST component interface outputs
- SinkCompare: used to compare Avalon-ST data interface component data with expected results
- SlaveComponent: used to verify the operation of a component that uses the Avalon-MM slave interface
- Timer: allows the host to time operations to a fine resolution
ATLANTiS Projects
An FPGA project is the integration of components to accomplish a specific task. ATLANTiS FrameWork includes the following projects:
Example Projects
- Anemone: demonstrates PCIe, DDR3, and Anemone interfaces †
- Typical: demonstrates integrated DDR3, SerDes, and PCIe on an S5 board †
Test Projects
- S5 LVDS: demonstrates the LVDS interface on S5 boards †
- S5 SerDes: demonstrates the different SerDes lanes on S5 family boards †
- S5/S4 DDR3: demonstrates the performance of simultaneous memory access of the board’s DDR3 banks †
- S5/S4 Integrated: shows all major external interfaces running at full bandwidth †
- S5/S4 PCIe: demonstrates the PCIe end point component †
- S4 FINe: demonstrates host access on the S4 family boards
- S4 MiscIO: simple I/O demonstration on S4 family boards
- S4 QDR2: demonstrates the QDR2 memory component and allows access to QDR2/+ memory on S4 boards
- GT/S4 DDIO: demonstrate the DDIO interface on the GT and S4 families of boards
- GT/GX/S4 SLite: demonstrates the different SerDes lanes on each of BittWare’s boards
- GT/GX DDR2: demonstrate the DDR2 interfaces on each of the BittWare Stratix II GX boards
- GT Links: demonstrates the link ports on BittWare GT family products containing the Analog Devices DSPs
* Contact BittWare for availability of these components.
† Contact BittWare for availability of Anemone and Stratix V based projects.
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