ATLANTiS FrameWork (AFW)

BittWare’s ATLANTiS FrameWork (AFW) provides reconfigurable FPGA components and the necessary infrastructure to implement, simulate, synthesize, validate, and deploy a complete FPGA application on BittWare’s Altera-based FPGA products.

AFW delivers fully validated physical interfaces for all board-level I/O communications, including high-speed SerDes and external memory access. To make the best use of these resources, the ATLANTiS FrameWork also includes reconfigurable resource management components that provide features such as DMA control and memory arbitration.

AFW components use Altera’s open standard Avalon Memory Mapped Interface to provide an addressed path to easily control and monitor ATLANTiS components using standard software. ATLANTiS FrameWork also uses Altera’s open standard Avalon Streaming Interface for high-speed point-to-point data transport between ATLANTiS components, allowing the ATLANTiS components to be easily connected. A set of reconfigurable fabric components facilitates both memory mapped and streaming data interconnect. These components, such as switches, decoders, FIFOs, and others, remove the burden of reinventing low-level IP for the FPGA, thus freeing ATLANTiS FrameWork users to focus on their unique value-added development.

Overcoming FPGA limitations.

When implementing an FPGA design in their systems, developers face the challenge of taking the FPGA from a blank slate to a fully functional implementation. They must carry the design from a set of specifications to the final phase in the development process – device-specific deployment. In the process, they will have to configure the FPGA’s logic blocks, connect resources, and set up the high-speed I/O.

An FPGA provides no peripheral infrastructure, which means developers must build everything from scratch, hand building physical interfaces for each board instantiation. The FPGA lacks a common API, and it only has a minimal amount of libraries, requiring developers to build all on-chip processing and control paths.

There is also no standard methodology for implementing an FPGA design. Even when using a pre-existing algorithm, the developer still needs to build low-level utility components. Modifying the design is both time-consuming and expensive. FPGA development also requires a specific skill set and specialized tools. All of these limitations add up to an often extended time to market.

A MicroProcessor approach.

AFW helps customers overcome the limitations of FPGA development and reduces their development costs by providing infrastructure that supports FPGA development at a higher abstraction level. By integrating validated HDL components, productivity enhancement resources, and software libraries, AFW moves customers quickly and confidently from design to deployment.

The AFW takes a software-like approach to FPGA development, raising the abstraction level by treating the FPGA like a System On a Chip (SOC) with peripheral infrastructure in place. AFW facilitates a software-like methodology to FPGA development by providing all the other necessary pieces to quickly create and modify simulation and synthesis projects.

Developers don’t have to start from scratch. They can leverage the existing streaming and memory-mapped interconnect fabrics, low level physical interfaces, and preexisting projects, complete with board-specific I/O configuration and physical interface timing constraints.

To promote design and hardware reuse, AFW leverages Altera’s Avalon standard to implement common interfaces for data and control. All of the AFW-provided components are reconfigurable and come with supporting software libraries (BWIO). AFW also uses a standard component structure, allowing straightforward integration of third-party components.

And it works. On proven, validated, COTS boards.