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Reconfigurable HDL components and supporting software development libraries
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Supports flexible, static, and run-time reconfiguration
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Low-level physical interfaces and timing constraints
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Standard component structure
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Uses common open standard streaming and memory mapped interconnect fabrics
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Allows straight-forward integration of third-party components
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Designs are portable to different Altera FPGAs and BittWare boards
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Standardized simulation and test resources
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Simulation and synthesis scripts to generate projects and I/O configuration
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Works with proven, validated COTS boards
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Example and template projects
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Supporting software libraries