ATLANTiS™ FrameWork [AFW]

Overview

ATLANTiS FrameWork (AFW) provides FPGA board support IP and integration for BittWare’s Altera FPGA-based COTS boards. A library of FPGA components that includes preconfigured physical interfaces, infrastructure, and examples, AFW drastically cuts development time and can be easily integrated into existing FPGA development environments. Working example projects for each supported board, which illustrate how to move data between the board’s different interfaces, along with full simulation and synthesis example projects allow customers to have a board up and running within hours. AFW includes all source code and is provided with our BittWorks II Toolkit.

Physical Interface Components

AFW includes all the physical interface components necessary for providing board-specific external I/O interfaces. In a typical FPGA design, physical interface development can account for the majority of the development time, but using AFW’s pre-configured physical interface components saves months of design effort. The physical interfaces are verified and performance tested and have been configured to meet the specific requirements of each BittWare FPGA-based board. Many of the AFW physical interfaces are Altera IP cores with a component wrapper to configure them for the BittWare board, ensuring that the IP is optimized for both the FPGA and the board.

Optional Component Library

To help further reduce integration time, AFW includes a library of optional components for system, interconnect, and simulation and test. Each component in AFW uses a standard API for communication: the Altera Avalon Streaming and Memory Mapped interfaces. By using a common interface, components become more reusable and portable.

Board I/O and Timing Constraints

AFW includes board-level projects to define all board-specific details for each supported product. These scripts define the resources available to the FPGA for each board, including I/O constraints, device-specific configuration, pin locations, and voltage levels.

Example Projects

Example Quartus projects designed for each board illustrate how to move data between the each of the board’s interfaces. These projects provide a starting point or reference for new development and are complete with a full simulation, proper project setup, simulation and synthesis scripts, complete I/O and timing constraints, and board test software.

ModelSim Simulations

AFW also includes full ModelSim simulations, which include scripted simulation control; standard data generators such as random, sine, cosine, sequence, pattern, file; verification and diagnostic components; and Bus Functional Models (BFM) for each physical interface, including memory models. These simulation resources allow developers to simulate the whole FPGA project, saving the time and cost of developing these resources themselves.

Software Components and Drivers

AFW is tightly integrated with BittWare’s BWIO software library. A collection of device drivers and utilities, BWIO provides control over the ATLANTiS FrameWork. BWIO also allows convenient access to other resources on the target board. It provides this control over both the board and FPGA resources in a way that is multiprocessor and multi-process safe. By allowing complicated operations to be performed with a minimum of operational code, it saves developers even more time by taking care of the sharing of board and FPGA resources between multiple processes.

Example of a System Architecture Featuring AFW
By providing the entire standard infrastructure that supports FPGA development, ATLANTiS FrameWork lets customers focus on developing their unique processing components (application user processing, application user interface, and user development modules) rather than on the infrastructure around it.

AFW Physical Interface Components
Standard DDR3 DDR2 QDR2/+ PCIe SerialLite GigE LVDS SerDes Double Data Rate I/O	Device Specific Anemone Link Port TigerSHARC Cluster Bus TigerSHARC Link Port FINe

AFW Workflow

The diagram below illustrates how ATLANTiS FrameWork fits into the traditional COTS FPGA development process. Items in blue show the steps that are already implemented in AFW. By providing the entire standard infrastructure that supports FPGA development, ATLANTiS FrameWork lets customers focus on developing their unique processing components rather than on the infrastructure around them.

ATLANTiS FrameWork provides proven resources that can reduce FPGA development efforts by months. It includes pre-configured physical interfaces, an extensive component library, and many examples that enable you to get an FPGA project running on your board with minimal effort. It fits into your existing FPGA development process, minimizing risk and eliminating the learning curve of adopting a new methodology. An essential piece to working with the FPGA on BittWare’s FPGA-based boards, AFW is packaged with BittWare’s BittWorks II Toolkit.

Features

AFW Includes

• Physical interface components for each board

• Library of optional components for system, interconnect, simulation, and test

• Board, I/O, and timing constraints

• Example Quartus projects

• Full ModelSim simulations

• Software components and drivers

AFW Benefits

Time Savings

• Pre-configured physical interface components save months of development time

• Board-level components define I/O pinouts and timing for each supported board

Flexibility

• Use only the components you need

• Uses a common interface specification (Avalon)

• Included source code allows customization

Ease of Use

• Example projects enable out of the box board operation

• Works with your existing FPGA development environment

Risk Reduction

• Mature, well-tested code base with full component and project simulations

• All source code is included

Specs

ATLANTiS Component Library

An ATLANTiS FrameWork component is an FPGA element that offers a predefined service. It is able to communicate with other components through a well-defined interface and thus, when connected to other components, the services work together to build complete projects. The ATLANTiS FrameWork component library includes the following:

Physical Interfaces

• AnemoneLinkPort:Converts an Anemone physical interface to Avalon-MM Master/Slave interfaces

• DDR3Memory:provides the DDR3 memory controller and physical interface to access external memory

• DDR2Memory:provides the DDR2 memory controller and physical interface to access external memory

• DDIOMaster:general purpose DDIO based interface for transferring memory mapped command and status board to board or device to device

• DDIOSlave:general purpose DDIO based interface for transferring Avalon-MM slave interface transactions board to board or chip to chip

• RxDDIO:uses Altera’s double data rate (DDR) I/O primitive for general purpose data transfer

• TxDDIO:uses Altera’s double data rate (DDR) I/O primitive for general purpose data transfer

• QDR2Memory:allows access to QDR2/QDR2+ memory on BittWare boards

• SPIMaster: masters a SPI bus with a user-configurable number of slaves

• FINe:interfaces to the FINe on BittWare boards

• FractionalPLL:derives custom internal clocks from external clocks (S5 boards)

• PLL:derives custom internal clocks from external clocks (S4, GT, GX boards)

• RxLinkPort:allows FPGA to receive data from a TigerSHARC link port

• TxLinkPort:sends data to a TigerSHARC link port

• ClusterBus:responsible for communication from Analog Devices’ TigerSHARC and/or FINe processors

Streaming Data Interconnect

• FIFO:can be configured to different bit widths and depths or to operate in multi-rate or single-rate mode

• MasterFIFO:bridge between two components that have master interfaces operating in different clock domains

• MasterPipeline:adds pipeline stages to an Avalon-MM master interface

• SlavePipeline:adds pipeline stages to an Avalon-MM slave interface

• Pipeline:adds pipeline stages to an Avalon-ST interface

• MasterReshape:allows communication between Avalon-MM master interfaces with different configurations

• MultiMasterDecoder:connects two or more Avalon-MM slave interfaces to an Avalon-MM master interface

• SlaveReshape:allows communication between Avalon-MM slave interfaces with different configurations

• Reshape:restructures streaming data to different bit widths and data rates

• SlaveBuffer:combines SlaveReshape with SlaveFIFOs

• SlaveBuffer:converts the input/output master interfaces to slave interfaces and instantiates a SlaveBuffer

• SlaveBurstAdapter:converts single word Avalon-MM transactions into Avalon-MM burst transactions

• SlaveToStreaming:converts an Avalon-MM slave interface to an Avalon-ST interface

• SlaveWriteToStreaming:converts Avalon-MM slave write transactions to Avalon-ST source transactions

• StreamingBuffer:allows streaming data input and output flexibility while reducing the amount of redundant code supporting each streaming component interface

• StreamingToMaster:converts Avalon streaming data transactions to Avalon-MM master read and write transactions

• StreamingToSlaveReadRsp:translates Avalon-ST input data to an Avalon-MM slave read response

• StreamingToSlaveSubSystem:moves data between Avalon-ST and Avalon-MM interfaces

• Switch:can connect any number of inputs to any number of outputs and can be configured to operate in multiple modes: static, priority, simple mux, bursting, etc.

Control and Memory Management

• Arbiter:provides multiple access from a varied number of slaves to a single Avalon-MM interface

• DMAController:Generates Avalon-MM DMAs by utilizing multiple DMAReader and/or DMAWriter engines

• DMAReader:performs DMA reads from an Avalon-MM slave and writes the response to an Avalon-ST source interface

• DMAWriter:performs DMA writes to an Avalon-MM slave interface sourced by an Avalon-ST interface

• MasterDMAReader:performs DMA reads from an Avalon-MM master and writes the response to an Avalon-ST source interface

• MasterDMAWriter:performs DMA writes to an Avalon-MM master interface sourced by an Avalon-ST interface

• IRQDecoder:decodes Avalon-IRQ sender interrupts

• Memory:provides a wrapper around the FPGA device specific RAM memory core

• MasterDecoder:decodes Avalon-MM master addresses to multiple Avalon-MM slaves

• MemoryMappedTester:automates the testing of an Avalon-MM slave interface

• Nios:wrapper around the Altera Nios processor allowing users to implement it without the use of SOPC Builder

• PacketDMAController:Generates Avalon-ST DMAs by utilizing multiple PacketDMAReader and/or PacketDMAWriter engines

• PacketDMAReader:performs DMA reads from an Avalon-ST packet interface and writes the response to an Avalon-ST typical interface

• PacketDMAWriter:

• PacketGenerator:test component that generates a stream of AFW Packets

• PacketSwitch:routes AFW Avalon-ST packets between different packet nodes within the FPGA

• PacketTargetMaster:accepts and converts AFW Avalon-ST packets to Avalon-MM transactions

• RegisterBank:used to manage component control, configuration, and status

• SlaveDecoder:decodes Avalon-MM slave addresses to multiple Avalon-MM slaves

• SlaveFIFO:a bidirectional Avalon-MM FIFO

• SlaveWindow:used to open up address space on an Avalon-MM bus

• StreamingTester:automates testing of a variable number of Avalon-ST input and output interfaces

• RxLVDS:high speed LVDS receiver that supports chip to chip communication and ADC/DAC interfaces

• TxLVDS:high speed LVDS transmitter that supports chip to chip communication and ADC/DAC interfaces

SerDes Protocols

• 10 GigE*:uses 10 GigE interface standard for high-speed data transfer

• PCIe:uses the Altera PCIe Hard IP core to provide a PCIe end point solution

• SerialLite:uses the Altera SerialLite II solution for high-speed SerDes transfer

• SerialRapidIO*:uses the Serial RapidIO standard for high-speed SerDes transfer

Example Components

• ComponentTemplate:skeleton of a VHDL file that can be used as a starting point for new development

• ExampleComponent:used as a reference for new developers to describe how to set up and configure a component

• ExampleSubSystem:demonstrates how to tie together streaming data paths with memory mapped data paths

Utility Libraries and Resources

• AvalonPkg:defines all supported Avalon interface profiles

• BoardInfoPkg:contains all board and device specifications

• Counter:basic programmable counter that can be used as a subcomponent

• ComponentPkg:contains a constant component ID for each ATLANTiS FrameWork component

• SoftReset:used to generate a soft reset signal synchronized to the provided input clock

• SynchPulse:used to synchronize a pulse across two different clock domains

• SynchRegister:assists in crossing clock domains, typically in a control data path

• SynchReset:used to retime asynchronous resets to a given time domain

• UtilityPkg:contains functions, procedures, and constants to aid in development

Simulation and Test

• AvalonSTFileReader:used to read a data input file during simulation and create Avalon-ST transactions that drive the component under test

• AvalonSTFileWriter:captures the results from the Avalon-ST interface of the component under test and writes the results to a file for validation and post processing

• ClkGen:used to create clocks for simulation at specified frequencies and phases

• HostTester:test a host interface

• PatternGenerator:creates all sorts of test patterns for simulation and board test

• SequenceGenerator:used to create different types of one- and two-dimensional sequences

• SimulationController:speeds up simulation efforts; reads a command file and translates it to an Avalon-MM master interface that is used to set up the component under test and other simulation components

• SinkComponent:validates/tests Avalon-ST component interface outputs

• SinkCompare:used to compare Avalon-ST data interface component data with expected results

• SlaveComponent:used to verify the operation of a component that uses the Avalon-MM slave interface

• StreamingTester:test Avalon-ST input and output interfaces

• Timer:allows the host to time operations to a fine resolution

ATLANTiS Projects

An FPGA project is the integration of components to accomplish a specific task. ATLANTiS FrameWork includes the following projects:

Example Projects

• S4 AAFM:example project for using the AAFM on an S4 board

• Typical:demonstrates integrated DDR3, SerDes, and PCIe on a GT board

Test Projects

• S5 Host:demonstrates the NIOS processor and dual port memory on the S5 board family

• S5/S4 DDR3:demonstrates the performance of simultaneous memory access of the board’s DDR3 banks

• S5/S4 LVDS:demonstrates the LVDS SerDes interface on the S5 and S4 board families

• S5/S4 PCIe:demonstrates the PCIe end point component

• S4 AAFM:test project for using the AAFM on an S4 board

• S4 Integrated:shows all major external interfaces running at full bandwidth

• S4 QDR2:demonstrates the QDR2 memory component and allows access to QDR2/+ memory on S4 boards

• S4/GT DDIO:demonstrate the DDIO interface on the GT and S4 families of boards

• S4/GT/GX SLite:demonstrates the different SerDes lanes on each of BittWare’s boards

• GT/GX DDR2:demonstrate the DDR2 interfaces on each of the BittWare Stratix II GX boards

• GT Links:demonstrates the link ports on BittWare GT family products containing the Analog Devices DSPs

† Contact BittWare for availability of Anemone and Stratix V based projects.
* Contact BittWare for availability of these components.

Ordering

ATLANTiS FrameWork is shipped with BittWare’s BittWorks II Toolkit.