Board Options

Looking for SmartNIC Shell on a low-profile board? Or do you need a larger logic footprint or perhaps HBM2 memory for your application? Our board solutions include any of the UltraScale+ boards (including low-profile with HBM2) on our Xilinx PCIe boards page linked here ↗.

SmartNIC Shell:
Jumpstart your 100G NIC project

While there are some 100G FPGA-enabled NICs commercially available, few offer any significant level of customization at the hardware level.

For those who desire such customization, we’ve introduced SmartNIC Shell—a solution designed to combine high-performance FPGA hardware with a solid suite of 100G NIC IP, including features like TimeServo for precision timestamping and DPDK (via Arkville) for standards-based host interaction at high bandwidth.

StreamSurge 100G network load testing

Do you need a solution without doing your own hardware customization? We also provide network products that are designed for end-users such as StreamSurge, a 100G network load tester built on the same IP and hardware as SmartNIC.
Learn more ↗

Quickly deploy anything that manipulates packets:

Network Functions (NFV)

Network Monitoring


Your Custom IP

Block diagram of major components.
Contact BittWare for additional detailed diagrams.

Match/Action Pipeline

This powerful component of the Shell allows for a combination of Match and Action blocks. In Match, packets are labeled in meta data as they flow through and then any number of Actions are applied based on those labels.

While users are free to customize other parts of the Shell, most will focus on this component using the supplied IP or their own customized match/action blocks.

Included Match/Action Blocks

  • An L2 match that fully implements DPDK L2 semantics
  • Drop/slice action for dropping all unmatched packets (those without labels) and optionally slice off payload bits

Xilinx SDNet Support | P4 Programming

With BittWare boards featuring Xilinx UltraScale+ FPGAs, users have access to SDNet—a powerful development environment for hardware-accelerated software-defined networks.

Benefits include:

  • Programmable through P4 model (
  • Flow-and-session-aware capabilities
  • Packet classification for security applications such as intrusion prevention and detection (IPS/IDS) and deep packet inspection (DPI)
  • Packet generation/checking for testing

Top Features

Quickly Build 100G NICs Focus your attention on your unique application, instead of re-inventing a NIC.
Match/Action Pipeline Ultra-low latency pattern matching with DPDK-compatible L2 filter. User-configurable or use as a basis for further customization.
Standardized kernel bypass for host interaction over PCIe. SmartNIC Shell provides DPDK offload to interact with host applications.
TimeServo Timestamping Precision time stamping including 1588-compatible clock adjustments. Uses TimeServo IP from Atomic Rules.
Xilinx UltraScale+ FPGA Large, powerful FPGAs with ample room for user IP. Selection of BittWare boards including traditional low-profile NIC size (XUPPL4) to 3/4-length boards with additional logic and memory options (XUPP3R).