Below are links to BittWare whitepapers
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• FFTs on the multi-core Anemone processor

This paper presents a description of a multi-core FFT implementation for BittWare’s Anemone processor. The Anemone floating-point FPGA co-processor has 16 Epiphany cores on an eMesh and is a very low-power highperformance DSP. A radix-4 FFT has been implemented in single core and multi-core configurations.

• Matrix multiplication on the multi-core Anemone processor

This paper presents an xGEMM (matrix multiplication) multi-core implementation on BittWare’s Anemone floating-point FPGA co-processor that has 16-core Epiphany cores on an eMesh. The Insight BLAS library contains single-core matrix multiplication SGEMM and CGEMM functions. These functions assume the matrix data is held in contiguous memory. For small dimensions, where the matrices data can be located in the DSP core local memory, the library routines provide exceptional performances. For large matrices that are located off-chip because they cannot be held fully in the local memory, even greater performances can be obtained through the use of the multiple DSP cores. This paper describes the single DSP core SGEMM routine and how to perform a multi-core SGEMM across the Anemone. The performance of the SGEMM and CGEMM routines are presented for both single core and multiple cores.

• Synchronisation barriers on the Anemone processor

Barrier functionality is required for a generic MIMD programming model to ensure the independent programs running on the separate cores synchronise at critical points in the application. This paper describes a multi-core barrier implementation for BittWare’s Anemone floating-point FPGA co-processor that has 16-core Epiphany cores on an eMesh. The barrier is implemented by creating software dependencies between the multiple cores in a tree structure. A tree structure minimises the latency of the barrier by minimising the number of layers the barrier signals have to pass through.

• FPGA Run-Time Reconfiguration: Two Approaches

Run-time reconfiguration for FPGA designs is an increasingly important requirement for many user markets, particularly military users who must adapt quickly to different threats and evolving communications waveforms. Run-time reconfiguration is defined as the ability to modify or change the functional configuration of the device during operation, through either hardware or software changes. This is an FPGA feature that is important to communications, military, and consumer applications as an approach to reducing component count and power consumption, by reusing the same FPGA for several functions. This paper introduces two approaches to FPGA run-time reconfiguration and discusses the strengths and weaknesses associated with each.

• An FPGA Framework Supporting Software Programmable Reconfiguration and Rapid Development of SDR Applications

  The role of FPGAs in Software Defined Radio (SDR) applications has continued to increase in spite of significant development costs. This paper introduces an FPGA framework leveraging concepts found in modern software applications. By utilizing software methodologies, this framework not only supports Software Programmable Reconfiguration (SPR) it also makes rapid development of FPGA-based SDR applications possible while decreasing costs and minimizing risk.

• Wireless Basestation Design Using Reconfigurable AMCs

  A wireless basestation is a good example of how one reconfigurable AMC can be used to provide the many building blocks of a complex wireless system. This paper discusses the requirements of wireless basestations and gives an example solution using a reconfigurable AMC.

• Extending the Flexibility of MicroTCA using Reconfigurable AMCs

  MicroTCA is an inherently flexible standard. When coupled with a reconfigurable AMC, this flexibility is enhanced, providing designers with an extensive array of options. This paper discusses what makes MicroTCA an inherently flexible standard, the requirement and definition of a reconfigurable AMC, and combining reconfigurable AMCs with custom backplanes to further extend this flexibility.

• BittWare TigerSHARC 6U CompactPCI Board vs. PowerPC G4 6U CompactPCI

  This paper discusses how the 6U CompactPCI Tiger board from BittWare, based on the 250 MHz ADSP TS101S TigerSHARC, offers substantial benefit to customers over PowerPC G4 based boards.