Interface ASICs Ease Time to Market

Jeffry Milrod
President, BittWare, Inc.

Traditionally, most embedded DSP subsystems have been implemented using fully custom, non-standard formats and interfaces. Although this ensures a well-optimized design for each specific application, building from scratch is costly, risky, and can greatly delay time to market. Using PCI as a standard bus for system communication and control facilitates the use of modular design, greatly simplifying system development as well as improving the reusability of software.

For years, the market has embraced the advantages (and inherent compromises) of using one of several standard PCI bus board formats (Slot-card, 6U Compact PCI, 3U Compact PCI, PCI Mezzanine Cards, and PC/104-Plus) as system-level building blocks. Since DSP is typically the most complex component in a system, this logic should apply especially well to the world of embedded DSP, allowing the DSP subsystem to be easily modified, enhanced, or upgraded with minimal impact to the rest of the system. This can be accomplished either through the use of commercial-of-the-shelf (COTS) DSP PCI boards, or by developing application-specific DSP boards with PCI bus interfaces.

DSP Board Integration Challenges

While the addition of PCI has opened the door to easier and more modular system design, its implementation can present significant challenges at the board level. At the core of the standard bus board market, industrial computing vendors have been able to aggressively attack this problem through the use of ASICs and chip-sets from the ultra-high volume personal computing world. There are a lot of chips out there to interface Intel and Motorola general-purpose processors to virtually anything; not so for DSP processors.

Further complicating the problem, most DSP chips do not have native PCI, and most DSP systems require multiple processors with lots of memory as well as signal interface I/O. Being special purpose processors, most DSPs also have limited peripheral sets, generally just a parallel bus, serial ports, and a few DMA engines. This requires board vendors to either glue together standard interface devices with the DSPs, or invest heavily in FPGAs and/or other PLDs to perform the interfacing.

Introduction of SHARC/PCI Solutions

For more than a decade, BittWare has focused exclusively on providing DSP subsystems based on the DSPs from Analog Devices. Recently, this has led to the development of a family of SHARC® FIN (Flexible Interface Node) ASICs that has, among other things, enabled the development of several COTS PCI bus DSP boards. In addition to interfacing the SHARC to PCI bus, the SharcFIN provides a comprehensive set of bus interfaces and peripherals for the SHARC DSPs that greatly simplify board-level design.

These SHARC DSP companion chips are supported by a broad range of software and are available from BittWare on COTS boards, application-specific boards, or as discrete chips. There are several incarnations of the SharcFIN to support the specific needs of the various SHARC DSPs. The versions that support the ADSP-21065L (SFIN-065) and the ADSP-21160 (SFIN-160) are currently in production; the versions that support the ADSP-21161 (SFIN-161) and the ADSP-TS101 (TFIN-101) are now in limited release with full production in the 2nd quarter of 2002.

Figure 1: Block diagram of simplified DSP board using SharcFIN ASIC

SHARC FIN Implementation Details

The first function of the SharcFIN must be to interface to the SHARC external port. This external bus varies across the SHARC family - bit width (32, 48, and 64-bits), timing, speed, and memory control - so the different versions of the SharcFIN are needed to interface to different SHARC buses. To better support the ADSP-21160, which has no internal support for SDRAM, the SharcFIN provides a full featured multi-bank SDRAM controller (as shown in the block diagram) that allows the SHARC to access SDRAM using burst mode access, providing low cost bulk memory up to 512MB - at sustained data rates of 400MB/sec.

The second most obvious function of the SharcFIN is to interface to PCI. Once again, variants rule. The high-end ADSP-21160 and ADSP-TS101 have 64-bit external ports and tremendous capacity for data flow. Therefore, the SharcFINs for these SHARCs implement a full 64-bit/66MHz master PCI interface. Conversely, the ADSP-21065L and ADSP-21161 have a 32-bit external port, and are targeted at low-cost applications; these SHARC FINs implement a 32-bit/33MHz or 32-bit/66MHz master PCI interface. Both implementations are PCI rev 2.2 compliant and provide 16 Bytes of configurable PCI mailbox registers.

A third bus interface is provided by the SharcFIN peripheral bus. This is a general-purpose utility bus that allows easy interface to standard microprocessor peripherals such as UARTs and FLASH memory. It provides a simple, glueless way to add additional functionality to a DSP board without perturbing the SHARC cluster bus. The I2C/Serial controller integrates some of the most common peripheral requirements right into the SharcFIN. Uses include data communications and SharcFIN interconnection as well as hardware configuration, test, and identification.

Figure 2: Photo of the SharcFIN ASIC

Since most board-level DSP implementations require multiple processors, all SharcFINs integrate an extensive interrupt and flag multiplexor. This programmable resource allows each SHARC to select the sources of its hardware interrupts; sources include other processors, PCI, peripherals, and the internal DMA engines. This capability facilitates system-level control and coordination of multiprocessors and can greatly simplify software development.

Perhaps the most powerful advantage of the SharcFIN is the data flow capabilities afforded by the integrated interfaces. The feature rich set of DMA engines and data buffer FIFOs support very high-speed, real-time data flow with a minimum of processor overhead. Thanks to this sophisticated integration and buffering, the SharcFIN can sustain the full PCI bandwidth of 528 MB/sec to or from the SHARCs and/or SDRAM, limited only by the speeds of the SHARC buses and memories. Advanced data movement capabilities such as fly-by DMA and chaining are also supported.

Of course, all of these features and capabilities would be virtually useless were it not for support software. BittWare's toolkits provide host interface libraries (HIL), debug monitors and diagnostics, drivers, and configuration software for Windowsä, Linux, and VxWorksä environments, as well as SHARC board support libraries and VisualDSP targets. Porting kits to other operating systems are also available. The SharcFINs are also I2O™ V1.5 compliant.

Ultimately, the SharcFIN allows SHARC DSPs to be quickly and easily integrated onto a PCI board. With its extensive software support, the SharcFIN allows board and systems designers to save time and money while reducing design risk.